參數(shù)資料
型號: MC100LVEP05MNTXG
廠商: ON Semiconductor
文件頁數(shù): 1/10頁
文件大小: 0K
描述: IC GATE AND/NAND 2INP 8-DFN
標準包裝: 1,000
系列: 100LVEP
邏輯類型: 與/與非門
電路數(shù): 1
輸入數(shù): 2 輸入(1,1)
施密特觸發(fā)器輸入:
輸出類型: 差分
電源電壓: 2.375 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-VFDFN 裸露焊盤
供應商設備封裝: 8-DFN(2x2)
包裝: 帶卷 (TR)
Semiconductor Components Industries, LLC, 2009
October, 2009 Rev. 2
1
Publication Order Number:
MC100LVEP05/D
MC100LVEP05
2.5V / 3.3V ECL 2-Input
Differential AND/NAND
Description
The MC100LVEP05 is a 2input differential AND/NAND gate.
The MC100LVEP05 is the low voltage version of the MC100EP05
and is functionally equivalent to the EL05 and LVEL05 devices. With
AC performance much faster than the LVEL05 device, the
MC100LVEP05 is ideal for low voltage applications requiring the
fastest AC performance available.
The 100 Series contains temperature compensation.
Features
220 ps Typical Propagation Delay
Input Clock Frequency > 3 GHz
0.2 ps Typical RMS Random Clock Period Jitter
LVPECL Mode Operating Range: VCC = 2.375 V to 3.6 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = 2.375 V to 3.6 V
Open Input Default State
Q Output Will Default LOW with Inputs Open
These are PbFree Devices*
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Y = Year
W = Work Week
G = PbFree Package
K = MC100
M = Date Code
A = Assembly Location
L = Wafer Lot
MARKING DIAGRAMS*
TSSOP8
DT SUFFIX
CASE 948R
ALYWG
G
KU05
1
8
1
8
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
DFN8
MN SUFFIX
CASE 506AA
4
(Note: Microdot may be in either location)
6N MG
G
1
8
KVP05
AYWWG
G
1
8
SOIC8
D SUFFIX
CASE 751
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