- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8746 > MC100LVE222FAG (ON Semiconductor)IC CLK BUFF DVDR MUX 2:15 52LQFP PDF資料下載
參數(shù)資料
| 型號： | MC100LVE222FAG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 0K |
| 描述： | IC CLK BUFF DVDR MUX 2:15 52LQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | 100LVE |
| 類型： | 扇出緩沖器（分配），除法器，多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:15 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | LVECL，LVPECL |
| 輸出： | ECL |
| 頻率 - 最大： | 1.5GHz |
| 電源電壓： | 3 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-LQFP |
| 供應(yīng)商設(shè)備封裝： | 52-LQFP（10x10） |
| 包裝： | 托盤 |
| 其它名稱： | MC100LVE222FAGOS |
Semiconductor Components Industries, LLC, 2007
November, 2007- Rev. 12
1
Publication Order Number:
MC100LVE222/D
MC100LVE222
3.3 V/5.0 VECL 1:15
Differential ÷1/÷2 Clock Driver
The MC100LVE222 is a low skew 1:15 differential
÷1/÷2 ECL
fanout buffer designed with clock distribution in mind. The
LVECL/LVPECL input signal pairs can be differential or used
single-ended (with VBB output reference bypassed and connected to the
unused input of a pair). Either of two fully differential clock inputs may
be selected. Each of the four output banks of 2, 3, 4, and 6 differential
pairs may be independently configured to fanout 1X or 1/2X of the
input frequency. The LVE222 specifically guarantees low output to
output skew. Optimal design, layout, and processing minimize skew
within a device and from lot to lot.
The fsel pins and CLK_Sel pin are asynchronous control inputs. Any
changes may cause indeterminate output states requiring an MR pulse
to resynchronize any 1/2X outputs.
The device tpd is affected by the quantity of output pairs terminated
with a minimum occurring with only one output pair and increasing
about 10-20 ps for all output pairs. Relative skew distribution is not
affected as more pairs are terminated, but the increased tpd does shift
the entire distribution. Unused output pairs should be left unterminated
(open) to reduce power and switching noise.
The MC100LVE222, as with most ECL devices, can be operated
from a positive VCC/VCCO supply in PECL mode. This allows the
LVE222 to be used for high performance clock distribution in +3.3 V
systems. Operation with >3.8 |(VCC or VCCO-VEE| span will require
special thermal handling considerations. Designers can take advantage
of the LVE222's performance to distribute low skew clocks across the
backplane or the board. In a PECL environment series or Thevenin line,
terminations are typically used as they require no additional power
supplies. All power supply pins must be connected. For more
information on using PECL, designers should refer to Application Note
AN1406/D. For a SPICE model, refer to Application Note AN1560/D.
Features
200 ps Part-to-Part Skew
50 ps Output-to-Output Skew
Selectable 1x or 1/2x Frequency Outputs
ESD Protection: >2 kV HBM, >200 V MM
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: VCC/VCCO = 3.0 V to 5.25 V with
VEE = 0 V
NECL Mode Operating Range: VCC/VCCO = 0 V with VEE = -3.0 V
to -5.25 V
Internal Input Pulldown Resistors
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 2
For Additional Information, refer to Application Note AND8003/D
Flammability Rating: UL 94 V-0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 684 devices
Pb-Free Packages are Available*
*For additional information on our Pb-Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
LQFP
FA SUFFIX
CASE 848D
MARKING DIAGRAM*
*For additional information, see Application Note
AND8002/D
1
52
A
= Assembly
Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb-Free
Package
MC100LVE
AWLYYWWG
222
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRD5410AIDTR-F | IC DAC 10BIT SRL 8SOIC |
| MC100LVEP14DTR2G | IC CLOCK BUFFER MUX 2:5 20-TSSOP |
| NB7L572MNG | IC CLK MUX XLATOR 4:2 8GHZ 32QFN |
| NB6L11DG | IC CLK BUFFER TRANSLA 1:2 8-SOIC |
| NB6L11DTG | IC CLK BUFFER TRANSLA 1:2 8TSSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100LVE222FAR2 | 功能描述:時鐘驅(qū)動器及分配 3.3V 1:15 Diff ECL RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC100LVE222FAR2G | 功能描述:時鐘驅(qū)動器及分配 BBG ECLClock Driver Differential RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC100LVE310FN | 功能描述:時鐘驅(qū)動器及分配 3.3V ECL 2:8 Diff RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC100LVE310FNG | 功能描述:時鐘驅(qū)動器及分配 3.3V ECL 2:8 Diff Fanout Buffer RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC100LVE310FNR2 | 功能描述:時鐘驅(qū)動器及分配 3.3V ECL 2:8 Diff RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。