參數(shù)資料
型號: MC100ES8111FA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 時鐘及定時
英文描述: 100E SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝: 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026BBA, LQFP-32
文件頁數(shù): 1/12頁
文件大?。?/td> 344K
代理商: MC100ES8111FA
Document Number: MC100ES8111
Rev 3, 09/2005
Freescale Semiconductor
Technical Data
Freescale Semiconductor, Inc., 2005. All rights reserved.
Low Voltage 1:10 Differential HSTL
Clock Fanout Buffer
The MC100ES8111 is a bipolar monolithic differential clock fanout buffer.
Designed for most demanding clock distribution systems, the MC100ES8111
supports various applications that require the distribution of precisely aligned
differential clock signals. Using SiGe technology and a fully differential
architecture, the device offers very low skew outputs and superior digital signal
characteristics. Target applications for this clock driver are high performance
clock distribution in computing, networking and telecommunication systems.
Features
1:10 differential clock fanout buffer
80 ps maximum device skew
SiGe technology
Supports DC to 625 MHz operation of clock or data signals
HSTL compatible differential clock outputs
PECL and HSTL compatible differential clock inputs
3.3 V power supply for device core, 1.5 V or 1.8 V HSTL output supply
Supports industrial temperature range
Standard 32 lead LQFP package
32-lead Pb-free package available
Functional Description
The MC100ES8111 is designed for low skew clock distribution systems and
supports clock frequencies up to 625 MHz. The device accepts two clock
sources. The CLK0 input accepts HSTL compatible signals and CLK1 accepts
PECL compatible signals. The selected input signal is distributed to 10 identical,
differential HSTL compatible outputs.
In order to meet the tight skew specification of the device, both outputs of a
differential output pair should be terminated, even if only one output is used. In
the case where not all 10 outputs are used, the output pairs on the same package
side as the parts being used on that side should be terminated.
The HSTL compatible output levels are generated with an open emitter
architecture. This minimizes part-to-part and output-to-output skew. The
open-emitter outputs require a 50
DC termination to GND (0 V). The output
supply voltage can be either 1.5 V or 1.8 V, the core voltage supply is 3.3 V. The
output enable control is synchronized internally preventing output runt pulse
generation. Outputs are only disabled or enabled when the outputs are already
in logic low state (true outputs logic low, inverted outputs logic high). The internal
synchronizer eliminates the setup and hold time requirements for the external
clock enable signal. The device is packaged in a 7x7 mm2 32-lead LQFP
package.
MC100ES8111
LOW-VOLTAGE 1:10
DIFFERENTIAL
HSTL CLOCK
FANOUT BUFFER
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-04
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-04
ORDERING INFORMATION
Device
Package
MC100ES8111FA
LQFP-32
MC100ES8111FAR2
LQFP-32
MC100ES8111AC
LQFP-32 (Pb-Free)
MC100ES8111ACR2
LQFP-32 (Pb-Free)
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相關代理商/技術(shù)參數(shù)
參數(shù)描述
MC100ES8111FAR2 制造商:Integrated Device Technology Inc 功能描述:CLOCK DRVR 2-IN HSTL 32LQFP - Tape and Reel
MC100H600FN 功能描述:轉(zhuǎn)換 - 電壓電平 9-Bit TTL to ECL RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8
MC100H600FNG 功能描述:轉(zhuǎn)換 - 電壓電平 9-Bit TTL to ECL RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8
MC100H600FNR2 功能描述:轉(zhuǎn)換 - 電壓電平 9-Bit TTL to ECL RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8
MC100H600FNR2G 功能描述:轉(zhuǎn)換 - 電壓電平 9-Bit TTL to ECL RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8