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| 型號(hào)： | MC100ES6222TBR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 100E SERIES, LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | PLASTIC, LQFP-52 |
| 文件頁(yè)數(shù)： | 6/9頁(yè) |
| 文件大小： | 314K |
| 代理商： | MC100ES6222TBR2 |
7
MC100ES6222
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
717
Table 7. AC Characteristics (ECL: VEE = -3.3V ± 5% or VEE = -2.5V ± 5%, VCC = GND) or
(PECL: VCC = 3.3V ± 5% or VCC = 2.5V ± 5%, VEE = GND, TJ = 0°C to +110°C)a
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Clock input pair CLK0, CLK0, CLK1, CLK1 (PECL or ECL differential signals)
VPP
Differential input voltageb (peak-to-peak)
0.2
1.3
V
VCMR
Differential input crosspoint voltagec
PECL
ECL
1.0
VEE+1.0
VCC - 0.3
-0.3V
V
fCLK
Input Frequency
0
2000
MHz
Differential
ECL/PECL clock outputs (QA[0:1], QA[0:1], QB[0:2], QB[0:2], QC[0:3], QC[0:3], QD[0:5], QD[0:5]
tPD
Propagation Delay
CLK0 or CLK1 to Qx
MR to Qx
670
820
970
ps
Differential
VO(P-P)
Differential output voltage (peak-to-peak)
fO < 1.0 GHz
fO < 2.0 GHz
TBD
mV
tsk(O)
Output-to-output skew
within QA[0:1]
within QB[0:2]
within QC[0:3]
within QD[0:5]
any output
35
50
60
130
ps
Differential
tsk(PP)
Output-to-output skew (part-to-part)
300
ps
Differential
tJIT(CC)
Output cycle-to-cycle jitter
TBD
ps
tSK(P)
DCO
Output pulse skewd
Output Duty Cycle
fREF < 0.1 GHz
fREF < 1.0 GHz
fREF < 2.0 GHz
49.85
48.50
47.00
5
50
15
50.15
51.50
53.00
ps
%
DCREF = 50%
tr, tf
Output Rise/Fall Time
50
300
ps
20% to 80%
a. AC characteristics apply for parallel output termination of 50
to VTT.
b. VPP (AC) is the minimum differential ECL/PECL input voltage swing required to maintain AC characteristics including tpd and device-to-de-
vice skew.
c. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the
VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propa-
gation delay, device and part-to-part skew.
d. Output pulse skew is the absolute difference of the propagation delay times: | tpLH – tpHL |.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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| MC100ES6254ACR2 | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 FSL Differential LVP ECL 2x2 Clock Switch RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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