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參數(shù)資料
| 型號： | MC100EP451FAR2 |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC REGISTER DIFF 6BIT ECL 32LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 100EP |
| 功能： | 主復(fù)位 |
| 類型： | D 型總線 |
| 輸出類型： | 差分 |
| 元件數(shù)： | 1 |
| 每個元件的位元數(shù)： | 6 |
| 觸發(fā)器類型： | 正邊沿 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | MC100EP451FAROSCT |
MC10EP451, MC100EP451
http://onsemi.com
6
Symbol
Characteristic
40°C
25°C
85°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
IEE
Power Supply Current
85
105
135
85
105
135
85
105
135
mA
VOH
Output HIGH Voltage (Note 14)
1145 1020
895
1145 1020
895
1145 1020
895
mV
OL
Output LOW Voltage (Note 14)
1945 1820 1695 1945 1820 1695 1945 1820 1695
mV
VIH
Input HIGH Voltage (SingleEnded)
1225
880
1225
880
1225
880
mV
VIL
Input LOW Voltage (SingleEnded)
1945
1625 1945
1625
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 15)
VEE+2.0
0.0
VEE+2.0
0.0
VEE+2.0
0.0
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
13.Input and output parameters vary 1:1 with VCC.
14.All loading with 50 W to VCC 2.0 V.
15.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 10. AC CHARACTERISTICS VCC = 0 V; VEE = 3.0 V to 5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 16)
Symbol
Characteristic
40°C
25°C
85°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
VOUTpp
Output Voltage Amplitude @ 3 GHz
540
670
520
650
450
580
mV
tPLH,
tPHL
Propagation Delay to
CLK to Q, Q
Output Differential
MR to Q, Q
330
430
530
630
350
450
550
650
390
490
590
690
ps
tRR
Reset Recovery
MR to CLK
240
145
250
150
260
160
ps
tS
tH
Setup Time
D to CLK
Hold Time
CLK to D
80
40
80
40
80
40
ps
tPW
Minimum Pulse Rate
MR
400
ps
tSKEW
WithinDevice Skew (Note 18)
DeviceToDevice Skew (Note 19)
20
35
40
100
20
35
40
100
20
35
40
100
tJITTER
CLOCK Random Jitter (RMS)
@ v3.0 GHz (Figure 4)
0.2
1
0.2
1
0.2
1
ps
tr
tf
Output Rise/Fall Times
Q, Q
(20% 80%)
100
150
250
110
160
260
130
180
280
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
16.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC 2.0 V.
17.VOL and VOH specifications not guaranteed for Fmax testing.
18.Skew is measured between outputs under identical transitions and conditions on any one device.
19.DeviceToDevice skew for identical transitions at identical VCC levels.
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| MC100EP451FAR2G | 功能描述:觸發(fā)器 3.3V/5V ECL 6-Bit Diff w/Master Reset RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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| MC100EP451MNR4G | 功能描述:觸發(fā)器 BBG ECL RESET RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| MC100EP51 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:3.3V / 5V ECL D Flip−Flop with Reset and Differential Clock |
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