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參數(shù)資料
| 型號： | MC100EP29MNG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLIP FLOP DATA/CLK D 20-QFN |
| 標(biāo)準(zhǔn)包裝： | 92 |
| 系列： | 100EP |
| 功能： | 設(shè)置（預(yù)設(shè)）和復(fù)位 |
| 類型： | D 型 |
| 輸出類型： | 差分 |
| 元件數(shù)： | 2 |
| 每個元件的位元數(shù)： | 1 |
| 頻率 - 時鐘： | 3GHz |
| 延遲時間 - 傳輸： | 420ps |
| 觸發(fā)器類型： | 正邊沿 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤 |
| 包裝： | 管件 |
Semiconductor Components Industries, LLC, 2009
June, 2009 Rev. 8
1
Publication Order Number:
MC10EP29/D
MC10EP29, MC100EP29
3.3V / 5VECL Dual
Differential Data and Clock
D Flip-Flop With Set and
Reset
Description
The MC10/100EP29 is a dual masterslave flipflop. The device
features fully differential Data and Clock inputs as well as outputs.
The MC10/100EP29 is functionally equivalent to the
MC10/100EL29. Data enters the master latch when the clock is LOW
and transfers to the slave upon a positive transition on the clock input.
The differential inputs have special circuitry which ensures device
stability under open input conditions. When both differential inputs
are left open the D input will pull down to VEE and the D input will
bias around VCC/2. The outputs will go to a defined state, however the
state will be random based on how the flip flop powers up.
Both flip flops feature asynchronous, overriding Set and Reset
inputs. Note that the Set and Reset inputs cannot both be HIGH
simultaneously.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
Features
Maximum Frequency > 3 GHz Typical
500 ps Typical Propagation Delays
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = 3.0 V to 5.5 V
Open Input Default State
Safety Clamp on Inputs
These are PbFree Devices
MARKING
DIAGRAM*
TSSOP20
DT SUFFIX
CASE 948E
XXXX
= MC10 or 100
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
http://onsemi.com
(Note: Microdot may be in either location)
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
XXXX
EP29
ALYWG
G
1
20
QFN20
MN SUFFIX
CASE 485E
XXXX
EP29
ALYWG
G
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100EP29MNTXG | 功能描述:觸發(fā)器 BBG ECL DL DIFF DFF W/SET RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| MC100EP31 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:3.3V / 5V ECL D Flip−Flop with Set and Reset |
| MC100EP31D | 功能描述:觸發(fā)器 3.3V/5V ECL D-Type RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| MC100EP31DG | 功能描述:觸發(fā)器 3.3V/5V ECL D-Type w/Set And Reset RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| MC100EP31DG | 制造商:ON Semiconductor 功能描述:FLIP FLOP LOGIC IC |
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