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參數(shù)資料
| 型號： | MC100EP196FAR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 3/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 1024TAP 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | 100EP |
| 標(biāo)片/步級數(shù)： | 1024 |
| 功能： | 可編程 |
| 延遲到第一抽頭： | 2.36ns |
| 接頭增量： | 10ps |
| 可用的總延遲： | 2.36ns ~ 12.258ns |
| 獨立延遲數(shù)： | 1 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | MC100EP196FAR2GOS |
MC100EP196
http://onsemi.com
11
Table 11. AC CHARACTERISTICS VCC = 0 V; VEE = 3.0 V to 3.6 V or VCC = 3.0 V to 3.6 V; VEE = 0 V (Note 8)
Symbol
Characteristic
40°C
25°C
85°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fmax
Maximum Frequency
1.2
GHz
tPLH
tPHL
Propagation Delay
IN to Q; D(09) = 0
IN to Q; D(09) = 1023
EN to Q; D(09) = 0
D10 to CASCADE
1810
9500
1780
350
2210
11496
2277
450
2610
13500
2780
550
1960
10000
1930
380
2360
12258
2430
477
2760
14000
2930
580
2180
10955
2150
420
2580
13454
2650
520
2980
15955
3150
620
ps
tRANGE
Programmable Range
{D(09) = HI} {D(09) = LO}
8600
9285
10000
9200
9897
10700
9900
10875 12000
ps
Dt
Step Delay (Note 9)
D0 High
D1 High
D2 High
D3 High
D4 High
D5 High
D6 High
D7 High
D8 High
D9 High
90
245
530
1060
2160
4335
7
23
39
58
137
293
590
1158
2317
4647
185
335
650
1265
2490
5010
100
260
560
1130
2290
4590
11
30
48
67
149
313
629
1237
2472
4955
200
370
710
1355
2680
5385
90
270
600
1200
2450
4935
13
32
53
73
154
337
681
1353
2712
5440
225
410
770
1520
3015
6015
ps
Mono
Monotonicity (Note 10)
ps
tSKEW
Duty Cycle Skew (Note 11)
|tPHLtPLH|
20
22
27
ps
ts
Setup Time
D to LEN
D to IN (Note 12)
EN to IN (Note 13)
150
100
150
10
130
105
150
100
150
70
150
120
150
100
150
70
165
140
ps
th
Hold Time
LEN to D
IN to EN (Note 14)
225
450
170
275
200
450
70
305
200
450
60
325
ps
tR
Release Time
EN to IN (Note 15)
SET MAX to LEN
SET MIN to LEN
150
400
300
105
70
165
150
400
350
120
110
180
150
400
350
140
160
205
ps
tjit
Random Clock Jitter
@ 1.2 GHz, SETMAX Delay
3
ps
VPP
Input Voltage Swing
(Differential Configuration)
150
800
1200
150
800
1200
150
800
1200
mV
tr
tf
Output Rise/Fall Time
2080% (Q)
2080% (CASCADE)
85
100
110
150
130
200
95
110
120
160
145
210
110
125
135
175
160
225
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC 2.0 V.
9. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations
of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range.
10.The monotonicity indicates the increased delay value for each binary count increment on the control inputs D(09).
11. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.
12.This setup time defines the amount of time prior to the input signal the delay tap of the device must be set.
13.This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than
VCC 1425 mV to that IN/IN transition.
14.This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response
greater than VCC 1425 mV to that IN/IN transition.
15.This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets
the specified IN to Q propagation delay and transition times.
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