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參數(shù)資料
| 型號： | MC100EP196BMNR4G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 1024TAP 32-QFN |
| 標準包裝： | 1 |
| 系列： | 100EP |
| 標片/步級數(shù)： | 1024 |
| 功能： | 可編程 |
| 延遲到第一抽頭： | 2.5ns |
| 接頭增量： | 10ps |
| 可用的總延遲： | 2.5ns ~ 13ns |
| 獨立延遲數(shù)： | 1 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 32-QFN（5x5） |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | MC100EP196BMNR4GOSCT |
MC100EP196B
http://onsemi.com
15
MultiChannel Deskewing
The most practical application for EP196B is in multiple
channel delay matching. Slight differences in impedance and
cable length can create large timing skews within a highspeed
system. To deskew multiple signal channels, each channel can
be sent through each EP196B as shown in Figure 9. One signal
channel can be used as reference and the other EP196Bs can
be used to adjust the delay to eliminate the timing skews.
Nearly any highspeed system can be finetuned (as small as
10 ps) to reduce the skew to extremely tight tolerances.
EP196B
IN
Q
IN
Q
#1
EP196B
IN
Q
IN
Q
#2
EP196B
IN
Q
IN
Q
#N
Digital
Data
Control
Logic
Figure 9. Multiple Channel Deskewing Diagram
Measure Unknown High Speed Device Delays
EP196Bs provide a possible solution to measure the
unknown delay of a device with a high degree of precision.
By combining two EP196Bs and EP31 as shown in Figure
10, the delay can be measured. The first EP196B can be set
to SETMIN and its output is used to drive the unknown delay
device, which in turn drives the input of a D flipflop of
EP31. The second EP196B is triggered along with the first
EP196B and its output provides a clock signal for EP31.
The programmed delay of the second EP196B is varied to
detect the output edge from the unknown delay device.
If the programmed delay through the second EP196B is too
long, the flipflop output will be at logic high. On the other
hand, if the programmed delay through the second EP196B is
too short, the flipflop output will be at a logic low. If the
programmed delay is correctly finetuned in the second
EP196B, the flipflop will bounce between logic high and
logic low. The digital code in the second EP196B can be
directly correlated into an accurate device delay.
EP196B
IN
Q
IN
Q
#1
EP196B
IN
Q
IN
Q
#2
Unknown Delay
Device
Control
Logic
D
CLK
Q
EP31
CLOCK
Figure 10. Multiple Channel Deskewing Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100EP196FA | 功能描述:延遲線/計時元素 3.3V/5V ECL RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| MC100EP196FAG | 功能描述:延遲線/計時元素 3.3V/5V ECL Programmable Delay RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| MC100EP196FAG | 制造商:ON Semiconductor 功能描述:Delay Line IC |
| MC100EP196FAR2 | 功能描述:延遲線/計時元素 3.3V/5V ECL RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| MC100EP196FAR2G | 功能描述:延遲線/計時元素 3.3V/5V ECL Programmable Delay RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
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