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參數(shù)資料
| 型號： | MC100EP17MNTXG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 1/11頁 |
| 文件大小： | 0K |
| 描述： | IC RCVR/DRVR QUAD DIFF ECL 20QFN |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 系列： | 100EP |
| 邏輯類型： | 差分接收器/驅(qū)動(dòng)器 |
| 電源電壓： | 3 V ~ 5.5 V |
| 位數(shù)： | 4 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-QFN（4x4） |
| 包裝： | 帶卷 (TR) |
Semiconductor Components Industries, LLC, 2008
November, 2008 Rev. 8
1
Publication Order Number:
MC10EP17/D
MC10EP17, MC100EP17
3.3V / 5VECL Quad
Differential Driver/Receiver
Description
The MC10/100EP17 is a 4-bit differential line receiver based on the
EP17 device. The >3.0 GHz maximum frequency provided by the
high frequency outputs makes the device ideal for buffering of very
high speed oscillators.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The design incorporates two stages of gain, internal to the device,
making it an excellent choice for use in high bandwidth amplifier
applications.
Inputs of unused gates can be left open and will not affect the
operation of the rest of the device. All VCC and VEE pins must be
externally connected to power supply to guarantee proper operation.
The 100 Series contains temperature compensation.
Features
220 ps Typical Propagation Delay
Maximum Frequency >3.0 GHz Typical
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = 3.0 V to 5.5 V
Open Input Default State
Safety Clamp on Inputs
Q Output Will Default LOW with Inputs Open or at VEE
VBB Output
PbFree Packages are Available*
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
TSSOP20
DT SUFFIX
CASE 948E
MARKING
DIAGRAMS*
XXX
= 10 or 100
A
= Assembly Location
L,
= Assembly Lot
WL
= Wafer Lot
Y, YY
= Year
W, WW = Work Week
G or G
= PbFree Package
SO20
DW SUFFIX
CASE 751D
1
20
1
20
MCXXXEP17
AWLYYWWG
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
(Note: Microdot may be in either loca-
tion)
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
XXXX
EP17
ALYWG
G
1
20
QFN20
MN SUFFIX
CASE 485E
MCXXX
EP17
ALYWG
G
1
20
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