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| 型號(hào)： | MC100EP140DR2G |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DETECT PHASE-FREQ ECL 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | 100EP |
| 類(lèi)型： | 相頻探測(cè)器 |
| PLL： | 無(wú) |
| 輸入： | CML，NECL，PECL |
| 輸出： | ECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無(wú)/是 |
| 頻率 - 最大： | 2GHz |
| 除法器/乘法器： | 無(wú)/無(wú) |
| 電源電壓： | ±3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOICN |
| 包裝： | 帶卷 (TR) |
Semiconductor Components Industries, LLC, 2006
November, 2006 Rev. 9
1
Publication Order Number:
MC100EP140/D
MC100EP140
3.3VECL PhaseFrequency
Detector
Description
The MC100EP140 is a three state phase frequencydetector
intended for phaselocked loop applications which require a minimum
amount of phase and frequency difference at lock. Since the part is
designed with fully differential internal gates, the noise is reduced
throughout the circuit, especially at high speeds. The basic operation
of a Phase/Frequency Detector (PFD) is to “compare” an incoming
signal (feedback) to a set reference signal. When the Reference (R)
and Feedback (FB) inputs are unequal in frequency and/or phase, the
differential UP (U) and DOWN (D) outputs will provide pulse streams
which, when subtracted and integrated, provide an error voltage for
control of a VCO. Detector states of operation are shown in the
Figure 2 and the State Table.
The typical output amplitude of the EP140 is 400 mV, allowing
faster switching time and greater bandwidth. For proper operation, the
input edge rate of the R and FB inputs should be less than 5 ns.
More information on Phase Lock Loop operation and application
can be found in AND8040.
the typical termination in Figure 5.
Features
500 ps Typical Propagation Delay
Maximum Frequency > 2.1 GHz Typical
Fully Differential Internally
Advanced High Band Output Swing of 400 mV
Transfer Gain: 1.0 mV/Degree at 1.4 GHz
1.2 mV/Degree at 1.0 GHz
Rise and Fall Time: 100 ps Typical
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: VCC = 3.0 V to 3.6 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = 3.0 V to 3.6 V
Open Input Default State
PbFree Packages are Available
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
SOIC8
D SUFFIX
CASE 751
MARKING DIAGRAMS*
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
1
8
KP140
ALYW
G
1
8
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