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參數(shù)資料
| 型號： | MC100EP131FAR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLIP FLOP ECL QUAD 5V 32LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | 100EP |
| 功能： | 設(shè)置（預(yù)設(shè)）和復(fù)位 |
| 類型： | D 型總線 |
| 輸出類型： | 差分 |
| 元件數(shù)： | 4 |
| 每個元件的位元數(shù)： | 1 |
| 頻率 - 時鐘： | 3GHz |
| 延遲時間 - 傳輸： | 460ps |
| 觸發(fā)器類型： | 正邊沿 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | MC100EP131FAR2GOS |
Semiconductor Components Industries, LLC, 2006
November, 2006 Rev. 10
1
Publication Order Number:
MC10EP131/D
MC10EP131, MC100EP131
3.3V / 5VECL Quad D
FlipFlop with Set, Reset,
and Differential Clock
Description
The MC10/100EP131 is a Quad Masterslaved D flipflop with
common set and separate resets. The device is an expansion of the
E131 with differential common clock and individual clock enables.
With AC performance faster than the E131 device, the EP131 is ideal
for applications requiring the fastest AC performance available.
Each flipflop may be clocked separately by holding Common
Clock (CC) LOW and CC HIGH, then using the differential Clock
Enable inputs for clocking (C03, C03).
Common clocking is achieved by holding the differential inputs
C03 LOW and C03 HIGH while using the differential Common
Clock (CC) to clock all four flipflops. When left floating open, any
differential input will disable operation due to input pulldown resistors
forcing an output default state.
Individual asynchronous resets (R03) and an asynchronous set
(SET) are provided.
Data enters the master when both CC and C03 are LOW, and
transfers to the slave when either CC or C03 (or both) go HIGH.
The 100 Series contains temperature compensation.
Features
460 ps Typical Propagation Delay
Maximum Frequency > 3 GHz Typical
Differential Individual and Common Clocks
Individual Asynchronous Resets
Asynchronous Set
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = 3.0 V to 5.5 V
Open Input Default State
Safety Clamp on Inputs
Q Output Will Default LOW with Inputs Open or at VEE
PbFree Packages are Available
LQFP32
FA SUFFIX
CASE 873A
MARKING
DIAGRAM*
*For additional marking information, refer to
Application Note AND8002/D.
http://onsemi.com
MCxxx
EP131
AWLYYWWG
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
32
1
MCxxx
EP131
AWLYYWWG
G
1
QFN32
MN SUFFIX
CASE 488AM
xxx
= 10 or 100
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G = PbFree Package
(Note: Microdot may be in either location)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100EP131MNG | 功能描述:觸發(fā)器 BBG ECL 4BIT RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| MC100EP131MNR4G | 功能描述:觸發(fā)器 BBG ECL 4BIT RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| MC100EP139 | 制造商:ON Semiconductor 功能描述: |
| MC100EP139DT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 3.3V/5V ECL Clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MC100EP139DTG | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 3.3V/5V ECL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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