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參數(shù)資料
| 型號(hào)： | MC100EP016AFAR2G |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 12/13頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC COUNTER 8BIT SYNC ECL 32LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | 100EP |
| 邏輯類型： | 二進(jìn)制計(jì)數(shù)器 |
| 方向： | 上 |
| 元件數(shù)： | 1 |
| 每個(gè)元件的位元數(shù)： | 8 |
| 復(fù)位： | 異步 |
| 計(jì)時(shí)： | 同步 |
| 計(jì)數(shù)速率： | 1.4GHz |
| 觸發(fā)器類型： | 正，負(fù) |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | MC100EP016AFAR2GOS |
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MC100EP016A
http://onsemi.com
8
APPLICATIONS INFORMATION
Cascading Multiple EP016A Devices
For applications which call for larger than 8‐bit counters
multiple EP016As can be tied together to achieve very wide
bit width counters. The active low terminal count (TC)
output and count enable input (CE) greatly facilitate the
cascading of EP016A devices. Two EP016As can be
cascaded without the need for external gating, however for
counters wider than 16 bits external OR gates are necessary
for cascade implementations.
Figure 4 below pictorially illustrates the cascading of 4
EP016As to build a 32‐bit high frequency counter. Note the
EP01 gates used to OR the terminal count outputs of the
lower order EP016As to control the counting operation of
the higher order bits. When the terminal count of the
preceding device (or devices) goes low (the counter reaches
an all 1s state) the more significant EP016A is set in its count
mode and will count one binary digit upon the next positive
clock transition. In addition, the preceding devices will also
count one bit thus sending their terminal count outputs back
to a high state disabling the count operation of the more
significant counters and placing them back into hold modes.
Therefore, for an EP016A in the chain to count, all of the
lower order terminal count outputs must be in the low state.
The bit width of the counter can be increased or decreased
by simply adding or subtracting EP016A devices from
Figure 4 and maintaining the logic pattern illustrated in the
same figure.
The maximum frequency of operation for a cascaded
counter chain is set by the propagation delay of the TC output,
the necessary setup time of the CE input, and the propagation
delay through the OR gate controlling it (for 16-bit counters
the limitation is only the TC propagation delay and the CE
setup time). Figure 4 shows EP01 gates used to control the
count enable inputs, however, if the frequency of operation is
slow enough, a LVECL OR gate can be used. Using the worst
case guarantees for these parameters.
Figure 4. 32‐Bit Cascaded EP016A Counter
CLK
P0 to P7
TC
CLK
P0 to P7
TC
CLK
EP01
P0 to P7
MSB
EP016
Q0 to Q7
EP016
Q0 to Q7
EP016
PE
CE
LSB
EP016
PE
CE
LOAD
LO
CLK
EP01
TC
CLK
PE
CE
CLK
TC
CLK
PE
CE
CLK
Note that this assumes the trace delay between the TC
outputs and the CE inputs are negligible. If this is not the
case estimates of these delays need to be added to the
calculations.
Programmable Divider
The EP016A has been designed with a control pin which
makes it ideal for use as an 8‐bit programmable divider. The
TCLD pin (load on terminal count) when asserted reloads the
data present at the parallel input pin (Pn's) upon reaching
terminal count (an all 1s state on the outputs). Because this
feedback is built internal to the chip, the programmable
division operation will run at very nearly the same frequency
as the maximum counting frequency of the device. Figure 5
below illustrates the input conditions necessary for utilizing
the EP016A as a programmable divider set up to divide by
113.
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| MC100EP016AMNG | 功能描述:計(jì)數(shù)器移位寄存器 3.3V ECL 8BT COUNTER BBG ECL RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC100EP016AMNR4G | 功能描述:計(jì)數(shù)器移位寄存器 3.3V ECL 8BT COUNTER BBG ECL RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC100EP016FA | 功能描述:IC COUNTER 8BIT SYNC ECL 32LQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 -計(jì)數(shù)器，除法器 系列:100EP 產(chǎn)品變化通告:1Q2012 Discontinuation 30/Mar/2012 標(biāo)準(zhǔn)包裝:2,500 系列:74HC 邏輯類型:二進(jìn)制計(jì)數(shù)器 方向:上 元件數(shù):1 每個(gè)元件的位元數(shù):12 復(fù)位:異步 計(jì)時(shí):- 計(jì)數(shù)速率:50MHz 觸發(fā)器類型:負(fù)邊沿 電源電壓:2 V ~ 6 V 工作溫度:-55°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| MC100EP016FAG | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:3.3V / 5V ECL 8−Bit Synchronous Binary Up Counter |
| MC100EP016FAR2 | 功能描述:IC COUNTER 8BIT SYNC ECL 32LQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 -計(jì)數(shù)器，除法器 系列:100EP 產(chǎn)品變化通告:1Q2012 Discontinuation 30/Mar/2012 標(biāo)準(zhǔn)包裝:2,500 系列:74HC 邏輯類型:二進(jìn)制計(jì)數(shù)器 方向:上 元件數(shù):1 每個(gè)元件的位元數(shù):12 復(fù)位:異步 計(jì)時(shí):- 計(jì)數(shù)速率:50MHz 觸發(fā)器類型:負(fù)邊沿 電源電壓:2 V ~ 6 V 工作溫度:-55°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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