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參數(shù)資料
| 型號(hào)： | MC100EP016AFAG |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 2/13頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC COUNTER 8BIT SYNC ECL 32LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | 100EP |
| 邏輯類型： | 二進(jìn)制計(jì)數(shù)器 |
| 方向： | 上 |
| 元件數(shù)： | 1 |
| 每個(gè)元件的位元數(shù)： | 8 |
| 復(fù)位： | 異步 |
| 計(jì)時(shí)： | 同步 |
| 計(jì)數(shù)速率： | 1.4GHz |
| 觸發(fā)器類型： | 正，負(fù) |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-LQFP（7x7） |
| 包裝： | 托盤 |
| 其它名稱： | MC100EP016AFAGOS |
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MC100EP016A
http://onsemi.com
10
APPLICATIONS INFORMATION (continued)
EP01
Q0 to Q7
P0 to P7
CLK
TC
PE
CE
Figure 7. 32‐Bit Cascaded EP016A Programmable Divider
LO
CLK
MSB
LSB
EP016
EP01
Q0 to Q7
P0 to P7
EP016
CLK
TC
PE
CE
CLK
TC
PE
CE
CLK
TC
PE
CE
CLK
Figure 7 shows a typical block diagram of a 32‐bit divider
chain. Once again to maximize the frequency of operation
EP01 OR gates were used. For lower frequency applications
a slower OR gate could replace the EP01. Note that for a
16‐bit divider the OR function feeding the PE (program
enable) input CANNOT be replaced by a wire OR tie as the
TC output of the least significant EP016A must also feed the
CE input of the most significant EP016A. If the two TC
outputs were OR tied the cascaded count operation would
not operate properly. Because in the cascaded form the PE
feedback is external and requires external gating, the
maximum frequency of operation will be significantly less
than the same operation in a single device.
Maximizing EP016A Count Frequency
The EP016A device produces 9 fast transitioning single
ended outputs, thus VCC noise can become significant in
situations where all of the outputs switch simultaneously in
the same direction. This VCC noise can negatively impact
the maximum frequency of operation of the device. Since
the device does not need to have the Q outputs terminated to
count properly, it is recommended that if the outputs are not
going to be used in the rest of the system they should be left
unterminated. In addition, if only a subset of the Q outputs
are used in the system only those outputs should be
terminated. Not terminating the unused outputs will not only
cut down the VCC noise generated but will also save in total
system power dissipation. Following these guidelines will
allow designers to either be more aggressive in their designs
or provide them with an extra margin to the published data
book specifications.
Figure 8. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D - Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
Q
D
Zo = 50 W
50
W
50
W
VTT
VTT = VCC - 2.0 V
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MC100EP016AFAG | 制造商:ON Semiconductor 功能描述:LOGIC IC |
| MC100EP016AFAR2 | 功能描述:計(jì)數(shù)器移位寄存器 3.3V/5V ECL 8-Bit RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC100EP016AFAR2G | 功能描述:計(jì)數(shù)器 IC 3.3V/5V ECL 8-Bit Up Counter RoHS:否 制造商:NXP Semiconductors 計(jì)數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計(jì)數(shù)法: 計(jì)數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| MC100EP016AMNG | 功能描述:計(jì)數(shù)器移位寄存器 3.3V ECL 8BT COUNTER BBG ECL RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC100EP016AMNR4G | 功能描述:計(jì)數(shù)器移位寄存器 3.3V ECL 8BT COUNTER BBG ECL RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
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