參數(shù)資料
型號: MC100EL05DTR2
廠商: ON Semiconductor
文件頁數(shù): 1/9頁
文件大?。?/td> 0K
描述: IC GATE AND/NAND ECL 2IN 8-TSSOP
產(chǎn)品變化通告: Product Discontinuation 20/Aug/2008
標(biāo)準(zhǔn)包裝: 2,500
系列: 100EL
邏輯類型: 與/與非門
電路數(shù): 1
輸入數(shù): 4 輸入(2,2)
施密特觸發(fā)器輸入:
輸出類型: 差分
電源電壓: 4.2 V ~ 5.7 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-TSSOP
包裝: 帶卷 (TR)
Semiconductor Components Industries, LLC, 2008
August, 2008 Rev. 6
1
Publication Order Number:
MC10EL05/D
MC10EL05, MC100EL05
5VECL 2‐Input Differential
AND/NAND
The MC10EL/100EL05 is a 2-input differential AND/NAND gate.
The device is functionally equivalent to the E404 device with higher
performance capabilities. With propagation delays and output transition
times significantly faster than the E404, the EL05 is ideally suited for
those applications which require the ultimate in AC performance.
Because a negative 2-input NAND is equivalent to a 2-input OR
function, the differential inputs and outputs of the device allows the EL05
to also be used as a 2-input differential OR/NOR gate.
The differential inputs employ clamp circuitry so that under open input
conditions (pulled down to VEE) the input to the AND gate will be
HIGH. In this way, if one set of inputs is open, the gate will remain active
to the other input.
The 100 Series contains temperature compensation.
Features
275 ps Propagation Delay
ESD Protection: > 1 kV Human Body Model,
> 100 V Machine Model
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = 4.2 V to 5.7 V
Internal Input Pulldown Resistors
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 44 devices
PbFree Packages are Available
1
2
3
45
6
7
8
D0
D1
VEE
Q
VCC
Figure 1. Logic Diagram and Pinout
Assignment
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAMS*
H = MC10
K = MC100
4O = MC10
2C = MC100
A = Assembly Location
KL05
ALYWG
G
SOIC8
D SUFFIX
CASE 751
1
8
TSSOP8
DT SUFFIX
CASE 948R
1
8
1
8
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
KEL05
ALYW
G
1
8
DFN8
MN SUFFIX
CASE 506AA
2C
M
G
14
HL05
ALYWG
G
1
8
HEL05
ALYW
G
1
8
4O
M
G
14
L
= Wafer Lot
Y = Year
W = Work Week
D = Date Code
G
= PbFree Package
(Note: Microdot may be in either location)
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