參數(shù)資料
型號: MC100E445FN
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: 4-BIT SERIAL/ PARALLEL CONVERTER
中文描述: 100E SERIES, 4-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PQCC28
封裝: PLASTIC, LCC-28
文件頁數(shù): 6/8頁
文件大小: 100K
代理商: MC100E445FN
MC10E445 MC100E445
MOTOROLA
ECLinPS and ECLinPS Lite
DL140 — Rev 4
6
Perhaps the easiest way to delay the second clock relative
to the first is to take advantage of the differential clock inputs
of the E445. By connecting the clock for the second E445 to
the complimentary clock input pin the device will clock a half
a clock period after the first E445 (Figure 7). Utilizing this
simple technique will raise the potential conversion
frequency up to 1.4GHz. The divide by eight clock of the
second E445 should be used to synchronize the parallel data
to the rest of the system as the parallel data of the two E445’s
will no longer be synchronized. This skew problem between
the outputs can be worked around as the parallel information
will be static for eight more clock pulses.
Figure 7. Extended Frequency 1:8 Demultiplexer
800ps
1150ps
CLOCK B
Tpd CLK
to SOUT
CLOCK A
700ps
(1.4GHz)
100ps
Q3
Q7
Q2
Q6
Q1
Q5
Q0
Q4
SIN
SIN
SOUT
SOUT
E445a
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
SIN
SIN
E445b
CLOCK
CLOCK
SERIAL
INPUT
DATA
PARALLEL OUTPUT DATA
Figure 8. Timing Diagram A. 1:8 Serial to Parallel Conversion
Dn-4
Dn-3
Dn-2
Dn-1
Dn
Dn+1
Dn+2
Dn+3
Dn-4
Dn-3
Dn-2
Dn-1
Dn
Dn+1
Dn+2
Dn+3
Dn-4
Dn-3
Dn-2
Dn-1
Dn
Dn+1
Dn+2
Dn+3
CLK
SINa
Q0
Q1
Q2
Q3
Q4 (Q0 a)
Q5 (Q1 a)
Dn-4
Dn-3
Dn-2
Dn-1
Dn
Dn+1
Q6 (Q2 a)
Q7 (Q3 a)
SOUTa
SOUTb
CL/4a
CL/4b
CL/8a
CL/8b
相關(guān)PDF資料
PDF描述
MC10E445 Replaced by TPS2057A : 0.345A, 2.7-5.5V Triple (2In/3Out) Hi-Side MOSFET, Fault Report, Act-High Enable 16-SOIC -40 to 85
MC10E445FN 4-BIT SERIAL/ PARALLEL CONVERTER
MC100E451FN 6-BIT D REGISTER DIFFERENTIAL DATA AND CLOCK
MC10E451 0.345A, 2.7-5.5V Triple (2In/3Out) Hi-Side MOSFET, Fault Report, Act-High Enable 16-SOIC 0 to 85
MC10E451FN 0.345A, 2.7-5.5V Triple (2In/3Out) Hi-Side MOSFET, Fault Report, Act-High Enable 16-SOIC 0 to 85
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