參數(shù)資料
型號: MC100E416FN
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: QUINT DIFFERENTIAL LINE RECEIVER
中文描述: LINE RECEIVER, PQCC28
封裝: PLASTIC, LCC-28
文件頁數(shù): 1/4頁
文件大小: 108K
代理商: MC100E416FN
LOGIC DIAGRAM
D3
D2
D2
VEE
VBB
D0
D0
26
27
28
2
3
4
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
5
6
7
8
9
10
D3
D4
D4
VCCO
Q4
Q4
VCCO
Q3
Q3
VCC
Q2
Q2
VCCO
Q1
D1
D1
VCCO
Q0
Q0
VCCO
Q1
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
VBB
1
Pinout: 28-Lead PLCC
(Top View)
* All VCC and VCCO pins are tied together on the die.
SEMICONDUCTOR TECHNICAL DATA
2–1
REV 2
Motorola, Inc. 1996
12/93
The MC10E416/100E416 is a 5-bit differential line receiving device.
The 2.0GHz of bandwidth provided by the high frequency outputs makes
the device ideal for buffering of very high speed oscillators.
A VBB pin is available to AC couple an input signal to the device. More
information on AC coupling can be found in the design handbook section
of this data book.
The design incorporates two stages of gain, internal to the device,
making it an excellent choice for use in high bandwidth amplifier
applications.
The differential inputs have internal clamp structures which will force
the Q output of a gate in an open input condition to go to a LOW state.
Thus, inputs of unused gates can be left open and will not affect the
operation of the rest of the device. Note that the input clamp will take
affect only if both inputs fall 2.5V below VCC.
Differential D and Q; VBB available
600ps Max. Propagation Delay
High Frequency Outputs
2 Stages of Gain
Extended 100E VEE Range of – 4.2V to – 5.46V
Internal 75k
Input Pulldown Resistors
PIN NAMES
Pin
Function
D
[
0:4
]
, D
[
0:4
]
Q
[
0:4
]
, Q
[
0:4
]
Differential Data Inputs
Differential Data Outputs
QUINT DIFFERENTIAL
LINE RECEIVER
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
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