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參數(shù)資料
| 型號(hào)： | MC100E404FNR2G |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC GATE AND/NAND QD DIFF 28-PLCC |
| 產(chǎn)品變化通告： | Dimensional change 21/Oct/2008 |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 系列： | 100E |
| 邏輯類型： | 與/與非門 |
| 電路數(shù)： | 4 |
| 輸入數(shù)： | 10 輸入（2，2，2，2，2） |
| 施密特觸發(fā)器輸入： | 無(wú) |
| 輸出類型： | 差分 |
| 電源電壓： | 4.2 V ~ 5.7 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 帶卷 (TR) |
Semiconductor Components Industries, LLC, 2006
November, 2006 Rev. 8
1
Publication Order Number:
MC10E404/D
MC10E404, MC100E404
5 VECL Quad Differential
AND/NAND
Description
The MC10E404/100E404 is a 4-bit differential AND/NAND
device. The differential operation of the device makes it ideal for pulse
shaping applications where duty cycle skew is critical. Special design
techniques were incorporated to minimize the skew between the upper
and lower level gate inputs.
Because a negative 2-input NAND function is equivalent to a
2-input OR function, the differential inputs and outputs of the device
also allow for its use as a fully differential 2 input OR/NOR function.
The output RISE/FALL times of this device are significantly faster
than most other standard ECLinPS devices resulting in an increased
bandwidth.
The differential inputs have clamp structures which will force the Q
output of a gate in an open input condition to go to a LOW state. Thus,
inputs of unused gates can be left open and will not affect the operation
of the rest of the device. Note that the input clamp will take affect only
if both inputs fall 2.5 V below VCC.
The 100 Series contains temperature compensation.
Features
Differential D and Q
700 ps Max. Propagation Delay
High Frequency Outputs
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = 4.2 V to 5.7 V
Internal Input 50 kW Pulldown Resistors
ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 200 V
Charged Device Model; > 2 kV
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level:
Pb = 1
PbFree = 3
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 274 devices
PbFree Packages are Available*
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING DIAGRAM*
xxx
= 10 or 100
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= PbFree Package
PLCC28
FN SUFFIX
CASE 776
MCxxxE404FNG
AWLYYWW
1
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
28
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