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參數(shù)資料
| 型號： | MC100E196FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | PROGRAMMABLE DELAY CHIP |
| 中文描述： | ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 148K |
| 代理商： | MC100E196FN |
SEMICONDUCTOR TECHNICAL DATA
2–1
REV 2
Motorola, Inc. 1996
12/93
The MC10E/100E196 is a programmable delay chip (PDC) designed
primarily for very accurate differential ECL input edge placement
applications.
The delay section consists of a chain of gates and a linear ramp delay
adjust organized as shown in the logic symbol. The first two delay
elements feature gates that have been modified to have delays 1.25 and
1.5 times the basic gate delay of approximately 80 ps. These two
elements provide the E196 with a digitally-selectable resolution of
approximately 20 ps. The required device delay is selected by the seven
address inputs D[0:6], which are latched on chip by a high signal on the
latch enable (LEN) control.
The FTUNE input takes an analog voltage and applies it to an internal
linear ramp for reducing the 20 ps resolution still further. The FTUNE input
is what differentiates the E196 from the E195.
An eighth latched input, D7, is provided for cascading multiple PDC’s
for increased programmable range. The cascade logic allows full control
of multiple PDC’s, at the expense of only a single added line to the data
bus for each additional PDC, without the need for any external gating.
2.0ns Worst Case Delay Range
≈
20ps/Delay Step Resolution
Linear Input for Tighter Resolution
>1.0GHz Bandwidth
On Chip Cascade Circuitry
Extended 100E VEE Range of –4.2 to –5.46V
75K
Input Pulldown Resistors
PIN NAMES
Pin
Function
IN/IN
EN
D[0:7]
Q/Q
LEN
SET MIN
SET MAX
CASCADE
FTUNE
Signal Input
Input Enable
Mux Select Inputs
Signal Output
Latch Enable
Min Delay Set
Max Delay Set
Cascade Signal
Linear Voltage Input
1
1
LOGIC DIAGRAM – SIMPLIFIED
VBB
IN
IN
EN
LEN
SET MIN
SET MAX
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
0
1
Q
Q
CASCADE
CASCADE
CASCADE
7 BIT LATCH
LEN
Q
LATCH
D
4 GATES
8 GATES
16 GATES
* 1.25
* 1.5
D0
D1
D2
D3
D4
D5
D6
D7
* DELAYS ARE 25% OR 50% LONGER THAN
*
STANDARD (STANDARD
≈
80 PS)
LINEAR
RAMP
FTUNE
PROGRAMMABLE
DELAY CHIP
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100E196FNG | 功能描述:延遲線/計時元素 5V ECL Programmable Delay RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| MC100E196FNR2 | 功能描述:延遲線/計時元素 5V ECL Programmable RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| MC100E196FNR2G | 功能描述:延遲線/計時元素 5V ECL Programmable Delay RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| MC100E210 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:5V ECL Dual 1:4, 1:5 Differential Fanout Buffer |
| MC100E210FN | 功能描述:時鐘緩沖器 5V ECL Dual 1:4 1:5 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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