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參數(shù)資料
| 型號(hào)： | MC100E137FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8-BIT RIPPLE COUNTER |
| 中文描述： | 100E SERIES, ASYN POSITIVE EDGE TRIGGERED 8-BIT UP BINARY COUNTER, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 117K |
| 代理商： | MC100E137FN |
SEMICONDUCTOR TECHNICAL DATA
2–1
REV 2
Motorola, Inc. 1996
7/96
The MC10E/100E137 is a very high speed binary ripple counter. The
two least significant bits were designed with very fast edge rates while the
more significant bits maintain standard ECLinPS
output edge rates.
This allows the counter to operate at very high frequencies while
maintaining a moderate power dissipation level.
1.8GHz Minimum Count Frequency
Differential Clock Input and Data Output Pins
VBB Output for Single-Ended Use
Internal 75k
Input Pulldown Resistors
Synchronous and Asynchronous Enable Pins
Asynchronous Master Reset
Extended 100E VEE Range of –4.2V to –5.46V
The device is ideally suited for multiple frequency clock generation as
well as a counter in a high performance ATE time measurement board.
Both asynchronous and synchronous enables are available to
maximize the device’s flexibility for various applications. The
asynchronous enable input, A_Start, when asserted enables the counter
while overriding any synchronous enable signals. The E137 features
XORed enable inputs, EN1 and EN2, which are synchronous to the CLK
input. When only one synchronous enable is asserted the counter
becomes disabled on the next CLK transition; all outputs remain in the
previous state poised for the other synchronous enable or A_Start to be
asserted to re-enable the counter. Asserting both synchronous enables
causes the counter to become enabled on the next transition of the CLK.
If EN1 (or EN2) and CLK edges are coincident, sufficient delay has been
inserted in the CLK path (to compensate for the XOR gate delay and the
internal D-flip flop setup time) to insure that the synchronous enable
signal is clocked correctly, hence, the counter is disabled.
The E137 can also be driven single-endedly utilizing the VBB output
supply as the voltage reference for the CLK input signal. If a single-ended
signal is to be used the VBB pin should be connected to the CLK input and
bypassed to ground via a 0.01
μ
F capacitor. VBB can only source/sink
0.5mA, therefore it should be used as a switching reference for the E137
only.
All input pins left open will be pulled LOW via an input pulldown resistor. Therefore, do not leave the differential CLK inputs
open. Doing so causes the current source transistor of the input clock gate to become saturated, thus upsetting the internal bias
regulators and jeopardizing the stability of the device.
The asynchronous Master Reset resets the counter to an all zero state upon assertion.
CLK
CLK
LOGIC DIAGRAM
Q
Q
CLK
CLK
D
R
Q
Q
CLK
CLK
D
R
EN1
EN2
CLK
CLK
A_Start
Q
Q
D
R
Q0
Q0
Q1
Q1
Q
Q
CLK
CLK
D
R
Q7
Q7
MR
VBB
8-BIT RIPPLE
COUNTER
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
CLK, CLK
Q0-Q7, Q0-Q7
A_Start
EN1, EN2
MR
VBB
Differential Clock Inputs
Differential Q Outputs
Asynchronous Enable Input
Synchronous Enable Inputs
Asynchronous Master Reset
Switching Refernce Output
PIN
FUNCTION
PIN NAMES
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100E137FNG | 功能描述:計(jì)數(shù)器移位寄存器 5V ECL 8-Bit Up/Down Counter RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC100E137FNG | 制造商:ON Semiconductor 功能描述:LOGIC IC |
| MC100E137FNR2 | 功能描述:計(jì)數(shù)器移位寄存器 5V ECL 8-Bit Up/Down RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC100E137FNR2G | 功能描述:計(jì)數(shù)器移位寄存器 5V ECL 8-Bit Up/Down Counter RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC100E141 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:8-BIT SHIFT REGISTER |
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