MC10E136, MC100E136
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2
D0
D3
D4
D5
VCCO
Q5
Q4
VCCO
Q3
Q2
VCC
VCCO
COUT
CLOUT
VCCO
Q1
Q0
VCCO
D1
MR
CLIN
CIN
CLK
VEE
S1
S2
D2
4
3
2
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
7
8
6
5
Pinout: 28-lead PLCC
(Top View)
* All VCC and VCCO pins are tied together on the die.
Figure 1. 28Lead Pinout
Warning: All VCC, VCCO, and VEE pins must be externally con-
nected to Power Supply to guarantee proper operation.
Table 1. PIN DESCRIPTION
PIN
FUNCTION
D0 D5
Q0 Q5
S1, S2
MR
CLK
COUT,
COUT
CLOUT
CIN
CLIN
VCC, VCCO
VEE
ECL Preset Data Inputs
ECL Data Outputs
Mode Control Pins
Master Reset
ECL Clock Input
ECL Differential Carry-Out Output (Active
LOW)
ECL Look-Ahead-Carry Out (Active LOW)
ECL Carry-In Input (Active LOW)
ECL Look-Ahead-Carry In Input (Active LOW)
Positive Supply
Negative Supply
Table 2. FUNCTION TABLE
(Expanded Truth Table on page
3)S1
S2
CIN
MR
CLK
FUNCTION
L
H
X
L
H
L
H
X
L
H
L
H
X
L
H
Z
X
Preset Parallel Data
Increment (Count Up)
Hold Count
Decrement (Count Down)
Hold Count
Reset (Qn = LOW)
Figure 2. E136 Universal Up/Down Counter Logic
Diagram
S1 S2
CIN
CLIN
MR
CLK
DQ
S
DQ
R
Q
DQ
R
Q
DQ
R
Q
DQ
S
Q
DQ
S
D0
Q0
D1
Q1
D2
D4
Q2
Q4
D5
Q5
COUT
QM0
QM1
QM0
COUT
CLOUT
Bits
2
4
Note
that
this
diagram
is
provided
for
understanding
of
logic
operation
only
.It
should
not
be
used
for
propagation
delays
as
m
any
gate
functions
are
achieved
internally
without
incurring
a
full
gate
delay