參數(shù)資料
型號: MC100E112FN
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: QUAD DRIVER
中文描述: 100E SERIES, QUAD 1-INPUT INV/NINV GATE, PQCC28
封裝: PLASTIC, LCC-28
文件頁數(shù): 1/4頁
文件大?。?/td> 99K
代理商: MC100E112FN
LOGIC DIAGRAM
VCCO
D3
D2
VEE
D1
D0
EN
26
27
28
2
3
4
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
5
6
7
8
9
10
Q3b
Q3a
Q3b
Q3a
VCCO
Q2b
Q2a
Q2b
Q2a
VCC
Q1b
Q1a
Q1b
Q1a
NC
VCCO
Q0a
Q0b
Q0a
Q0b
VCCO
D0
D1
D2
D3
EN
Q0a
Q0b
Q0a
Q0b
Q1a
Q1b
Q1a
Q1b
Q2a
Q2b
Q2a
Q2b
Q3a
Q3b
Q3a
Q3b
1
Pinout: 28-Lead PLCC
(Top View)
* All VCC and VCCO pins are tied together on the die.
SEMICONDUCTOR TECHNICAL DATA
2–1
REV 2
Motorola, Inc. 1996
12/93
The MC10E/100E112 is a quad driver with two pairs of OR/NOR
outputs from each gate, and a common, buffered enable input. Using the
data inputs the device can serve as an ECL memory address fan-out
driver. Using just the enable input, the device serves as a clock driver,
although the MC10E/100E111 is designed specifically for this purpose,
and offers lower skew than the E112. For memory address driver
applications where scan capabilities are required, please refer to the
E212 device.
600ps Max. Propagation Delay
Common Enable Input
Extended 100E VEE Range of – 4.2V to – 5.46V
75k
Input Pulldown Resistors
PIN NAMES
Pin
Function
D0 – D3
EN
Data Inputs
Enable Input
Qna, Qnb
Qna, Qnb
True Outputs
Inverting Outputs
QUAD DRIVER
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
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