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參數(shù)資料
| 型號： | MC100E016FNR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 10/12頁 |
| 文件大小： | 0K |
| 描述： | IC COUNTER 8BIT SYNC ECL 28PLCC |
| 產(chǎn)品變化通告： | Dimensional change 21/Oct/2008 |
| 標準包裝： | 500 |
| 系列： | 100E |
| 邏輯類型： | 二進制計數(shù)器 |
| 方向： | 上 |
| 元件數(shù)： | 1 |
| 每個元件的位元數(shù)： | 8 |
| 復位： | 異步 |
| 計時： | 同步 |
| 計數(shù)速率： | 900MHz |
| 觸發(fā)器類型： | 正邊沿 |
| 電源電壓： | 4.2 V ~ 5.7 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應商設備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 帶卷 (TR) |
MC10E016, MC100E016
http://onsemi.com
7
APPLICATIONS INFORMATION
Cascading Multiple E016 Devices
For applications which call for larger than 8bit counters
multiple E016s can be tied together to achieve very wide bit
width counters. The active low terminal count (TC) output
and count enable input (CE) greatly facilitate the cascading
of E016 devices. Two E016s can be cascaded without the
need for external gating, however for counters wider than 16
bits external OR gates are necessary for cascade
implementations.
Figure 3 below pictorially illustrates the cascading of 4
E016s to build a 32bit high frequency counter. Note the
E101 gates used to OR the terminal count outputs of the
lower order E016s to control the counting operation of the
higher order bits. When the terminal count of the preceding
device (or devices) goes low (the counter reaches an all 1s
state) the more significant E016 is set in its count mode and
will count one binary digit upon the next positive clock
transition. In addition, the preceding devices will also count
one bit thus sending their terminal count outputs back to a
high state disabling the count operation of the more
significant counters and placing them back into hold modes.
Therefore, for an E016 in the chain to count, all of the lower
order terminal count outputs must be in the low state. The bit
width of the counter can be increased or decreased by simply
adding or subtracting E016 devices from Figure 3 and
maintaining the logic pattern illustrated in the same figure.
The maximum frequency of operation for the cascaded
counter chain is set by the propagation delay of the TC
output and the necessary setup time of the CE input and the
propagation delay through the OR gate controlling it (for
16bit counters the limitation is only the TC propagation
delay and the CE setup time). Figure 3 shows EL01 gates
used to control the count enable inputs, however, if the
frequency of operation is lower a slower, ECL OR gate can
be used. Using the worst case guarantees for these
parameters from the ECLinPS data book, the maximum
count frequency for a greater than 16bit counter is
500 MHz and that for a 16bit counter is 625 MHz.
Note that this assumes the trace delay between the TC
outputs and the CE inputs are negligible. If this is not the
case estimates of these delays need to be added to the
calculations.
Figure 3. 32Bit Cascaded E016 Counter
EL01
CLOCK
P0 > P7
TC
CLK
P0 > P7
TC
CLK
EL01
P0 > P7
TC
CLK
P0 > P7
MSB
E016
PE
CE
Q0 > Q7
E016
PE
CE
Q0 > Q7
E016
PE
CE
LSB
E016
PE
CE
LO
LOAD
TC
CLK
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| MC100E101FNR2 | 功能描述:邏輯門 5V ECL Quad 4-Input RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| MC100E101FNR2G | 功能描述:邏輯門 5V ECL Quad 4-Input OR/NOR RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
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