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參數(shù)資料
| 型號(hào)： | MC-ACT-16550-VLOG |
| 元件分類(lèi)： | FPGA |
| 英文描述： | FPGA, XMA |
| 文件頁(yè)數(shù)： | 1/9頁(yè) |
| 文件大?。?/td> | 278K |
| 代理商： | MC-ACT-16550-VLOG |
INTERFACE
CONTROL
LOGIC
SHIFTLGC
DATA_IN[7:0]
SYNCHRS
STATE MACHINE
SHIFT
REGISTER
ENABLE
DATA_OUT[7:0]
(HOST DATA)
DATA_VLD
SCL_OUT
SDA_OUT
STDFAST_N
STATUS[5:0]
SCL
AT TOP LEVEL
SDA
CLK
SCL_IN
SDA_IN
START
RESET
ADDR_IN[6:0]
TWSI_CMD[2:0]
CFG[127:0]
REQ_DATA
FIRST_BYTE
AvnetCore: Datasheet
Two Wire Serial Interface
(TWSI)
Intended Use:
— Embedded microprocessor boards and any circuit needing I2C
peripherals
Features:
— Fully optimized for Actel FPGAs
— I2C-compatible two-wire serial interface core; I2C is a trademark
of Philips, Inc.
— Multi-master operation with arbitration and clock synchronization
— Slave transmit and receive operation
— Support for reads, writes, burst reads, burst writes, and repeated
start
— User-defined timing and clock frequency
— Fast mode and standard mode operation
Targeted Devices:
— Axcelerator Family
— ProASIC3 Family
— ProASICPLUS Family
Core Deliverables:
— Netlist Version
> Netlist compatible with the Actel Designer place and route tool
> Compiled RTL simulation model, compliant with the Actel
Libero environment
— RTL Version
> VHDL or Verilog RTL Source Code
> Test Bench
— All
> User Guide
> Data Sheet
Synthesis and Simulation Support:
— Synthesis: Synplicity
— Simulation: ModelSim
— Other tools supported upon request
Verification:
— Test Bench
The MC-ACT-TWSI is a “core” logic module specifically designed for Actel FPGAs that
emulates the functionality of the industry standard two-wire serial interface, I2C. This
core does not support 10-bit slave addressing or START byte data transfers. It
facilitates upgrading current systems by allowing the designer to incorporate the
TWSI function as well as other logic into a single, state of the art FPGA. This core is
designed such that it can be instantiated into a Actel design and “hooked up” to I/O
buffers and pads and then compiled to make a device that will “plug in” to a TWSI
application. The core can be configured to operate as either a Master-Slave, Master-
Only, or Slave-Only.
Block Diagram
Version 1.0, July 2006
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