參數(shù)資料
型號: MC-4R64FKE8D-840
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: Direct Rambus DRAM RIMM Module 64M-BYTE (32M-WORD x 18-BIT)
中文描述: 32M X 18 DIRECT RAMBUS DRAM MODULE, DMA184
封裝: RIMM-184
文件頁數(shù): 14/14頁
文件大?。?/td> 154K
代理商: MC-4R64FKE8D-840
EOL
Produ
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Data Sheet E0270N11 (Ver 1.1)
9
MC-4R64FKE8D-840
AC Electrical Specifications
Symbol
Parameter and Conditions
MIN.
TYP.
MAX.
Unit
Z
Module Impedance of RSL signals
25.2
28.0
30.8
Module Impedance of SCK and CMD signals
23.8
28.0
32.2
TPD
Average clock delay from finger to finger of all RSL clock nets
1.28
ns
(CTM, CTMN,CFM, and CFMN)
TPD
Propagation delay variation of RSL signals with respect to TPD
Note1,2
21
+21
ps
TPD-CMOS
Propagation delay variation of SCK signal with respect to an average clock
delay
Note1
250
+250
ps
TPD- SCK,CMD Propagation delay variation of CMD signal with respect to SCK signal
200
+200
ps
Vα/VIN
Attenuation Limit
12.0
%
VXF/VIN
Forward crosstalk coefficient
(300ps input rise time 20% - 80%)
2.0
%
VXB/VIN
Backward crosstalk coefficient
(300ps input rise time 20% - 80%)
1.5
%
RDC
DC Resistance Limit
0.6
Notes 1. TPD or Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM,
CTMN, CFM, and CFMN).
2. If the RIMM module meets the following specification, then it is compliant to the specification.
If the RIMM module does not meet these specifications, then the specification can be adjusted by the
“Adjusted
TPD Specification” table.
Adjusted
TPD Specification
Symbol
Parameter and conditions
Adjusted MIN./MAX.
Absolute
Unit
MIN.
MAX.
TPD
Propagation delay variation of RSL signals with respect to TPD
+/
[17+(18*N*Z0)] Note
30
+30
ps
Note
N = Number of RDRAM devices installed on the RIMM module.
Z0 = delta Z0% = (MAX. Z0 MIN. Z0) / (MIN. Z0)
(MAX. Z0 and MIN. Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers on
the module.)
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