參數(shù)資料
型號(hào): MC-4R128FKE6D-840
廠商: ELPIDA MEMORY INC
元件分類(lèi): DRAM
英文描述: Direct Rambus DRAM RIMM Module 128M-BYTE (64M-WORD x 16-BIT)
中文描述: 64M X 16 DIRECT RAMBUS DRAM MODULE, 40 ns, DMA184
封裝: SOCKET TYPE, RIMM-184
文件頁(yè)數(shù): 9/14頁(yè)
文件大?。?/td> 497K
代理商: MC-4R128FKE6D-840
9
E0261N10 (Ver. 1.0)
MC-4R128FKE6D-840
AC Electrical Specifications
Parameter and Conditions
MIN.
Z
Module Impedance of RSL signals
Module Impedance of SCK and CMD signals
T
PD
!"####$% !&
'
&
()*)+*),*"),+-
T
PD
Propagation delay variation of RSL signals with respect to TPD
Note1,2
21
+21
ps
T
PD-CMOS
Propagation delay variation of SCK signal with respect to an average clock
delay
Note1
250
+250
ps
T
PD- SCK,CMD
Propagation delay variation of CMD signal with respect to SCK signal
200
+200
ps
V
α
/V
IN
.%
'
/
V
XF
/V
IN
,0" &&! ##
(1&1.&/2/-
/
V
XB
/V
IN
Backward
&&! ##
(1&1.&/2/-
'
/
$
)
)$&& %
3
Notes 1.
T
PD
or Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM,
CTMN, CFM, and CFMN).
2.
If the RIMM module meets the following specification, then it is compliant to the specification.
If the RIMM module does not meet these specifications, then the specification can be adjusted by the
“Adjusted
T
PD
Specification” table.
Adjusted
T
PD
Specification
Symbol
Parameter and conditions
Adjusted MIN./MAX.
Absolute
Unit
MIN.
MAX.
T
PD
Propagation delay variation of RSL signals with respect to T
PD
45
6'74('8+8
9-:
30
+30
ps
Note
N = Number of RDRAM devices installed on the RIMM module.
Z0 = delta Z0
/
= (MAX. Z0
MIN. Z0) / (MIN. Z0)
(MAX. Z0 and MIN. Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers
on the module.)
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MC-4R128FKE6D-845 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:Direct Rambus DRAM RIMM Module 128M-BYTE (64M-WORD x 16-BIT)
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MC-4R128FKE8D-653 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:Direct Rambus DRAM RIMM Module 128M-BYTE (64M-WORD x 18-BIT)
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MC-4R128FKE8D-840 制造商:ELPIDA 制造商全稱(chēng):Elpida Memory 功能描述:Direct Rambus DRAM RIMM Module 128M-BYTE (64M-WORD x 18-BIT)