參數(shù)資料
型號(hào)： MC-4564DC726
廠商： NEC Corp.
英文描述： 64M-Word By 72-BIT Dynamic RAM Module(動(dòng)態(tài)RAM模塊)
中文描述： 6400 - Word的72位動(dòng)態(tài)內(nèi)存模塊（動(dòng)態(tài)內(nèi)存模塊）
文件頁(yè)數(shù)： 7/20頁(yè)
文件大?。?/td> 170K
代理商： MC-4564DC726
7
MC-4564DC726
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test condition
MIN.
MAX.
Unit
Notes
Operating current
I
CC1
Burst length
=
1
/CAS latency = 2
-A80
2,980
mA
1
t
RC
≥
t
RC(MIN.)
-A10
2,710
I
O
= 0
mA
/CAS latency = 3
-A80
3,070
-A10
2,800
Precharge standby current in I
CC2
P
CKE
≤
V
IL(MAX.)
, t
CK
=
15
ns
286
mA
power down mode
I
CC2
PS CKE
≤
V
IL(MAX.)
, t
CK
=
∞
28
Precharge standby current in
non power down mode
I
CC2
N
CKE
≥
V
IH(MIN.)
, t
CK
=
15
ns, /CS
≥
V
IH(MIN.)
,
Input signals are changed one time during 30
ns.
970
mA
I
CC2
NS CKE
≥
V
IH(MIN.)
, t
CK
=
∞
, Input signals are stable.
216
Active standby current in
I
CC3
P
CKE
≤
V
IL(MAX.)
, t
CK
=
15
ns
430
mA
power down mode
I
CC3
PS CKE
≤
V
IL(MAX.)
, t
CK
=
∞
144
Active standby current in
I
CC3
N
CKE
≥
V
IH(MIN.)
, t
CK
=
15
ns, /CS
≥
V
IH(MIN.)
,
1,150
mA
non power down mode
Input signals are changed one time during 30
ns.
I
CC3
NS CKE
≥
V
IH(MIN.)
, t
CK
=
∞
, Input signals are stable.
432
Operating current
I
CC4
t
CK
≥
t
CK(MIN.)
/CAS latency = 2
-A80
2,800
mA
2
(Burst mode)
I
O
= 0
mA
-A10
2,440
/CAS latency = 3
-A80
3,070
-A10
2,800
Refresh current
I
CC5
t
RC
≥
t
RC(MIN.)
/CAS latency = 2
-A80
5,680
mA
3
-A10
5,320
/CAS latency = 3
-A80
5,860
-A10
5,500
Self refresh current
I
CC6
CKE
≤
0.2
V
322
mA
Input leakage current
I
I(L)
V
I
=
0 to 3.6
V,
All other pins not under test =
0 V
–
20
+
20
μ
A
Output leakage current
I
O(L)
D
OUT
is disabled, V
O
=
0 to 3.6
V
–
3
+
3
μ
A
High level output voltage
V
OH
I
O
=
–
4.0
mA
2.4
V
Low level output voltage
V
OL
I
O
=
+
4.0
mA
0.4
V
Notes 1.
I
CC1
depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, I
CC1
is measured on condition that addresses are changed only one time during t
CK(MIN.)
.
2
. I
CC4
depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, I
CC4
is measured on condition that addresses are changed only one time during t
CK(MIN.)
.
3.
I
CC5
is measured on condition that addresses are changed only one time during t
CK(MIN.)
.
相關(guān)PDF資料
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MC-4564EC726 64 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE
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MC-4564EC726EFB-A10 64 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC-4564EC726 制造商:NEC 制造商全稱:NEC 功能描述:64 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE
MC-4564EC726EFB-A10 制造商:NEC 制造商全稱:NEC 功能描述:64 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE
MC-4564EC726EFB-A80 制造商:NEC 制造商全稱:NEC 功能描述:64 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE
MC-4564EC726PFB-A10 制造商:NEC 制造商全稱:NEC 功能描述:64 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE
MC-4564EC726PFB-A80 制造商:NEC 制造商全稱:NEC 功能描述:64 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE
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