參數(shù)資料
型號： MBM29PL32TM90TN-E1
廠商： SPANSION LLC
元件分類： PROM
英文描述： 2M X 16 FLASH 3V PROM, 90 ns, PDSO48
封裝： PLASTIC, TSOP1-48
文件頁數(shù)： 19/72頁
文件大小： 450K
代理商： MBM29PL32TM90TN-E1
Retired Product
DS05-20907-4E_July 31, 2007
MBM29PL32TM/BM90/10
26
Page Mode Read
The device is capable of fast read access for random locations within limited address location called Page. The
Page size of the device is 8 bytes / 4 words, within the appropriate Page being selected by the higher address
bits A20 to A2 and the address bits A1 to A0 in Word mode ( A1 to A-1 in Byte mode) determining the specific word
within that page. This is an asynchronous operation with the microprocessor supplying the specific word location.
The initial page access is equal to the random access (tACC) and subsequent Page read access (as long as the
locations specified by the microprocessor fall within that Page) is equivalent to the page address access time
(tPACC). Here again, CE selects the device and OE is the output control and should be used to gate data to the
output pins if the device is selected. Fast Page mode, accesses are obtained by keeping A20 to A2 constant and
changing A1 and A0 in Word mode ( A1 to A-1 in Byte mode ) to select the specific word within that Page.
Output Disable
With the OE input at logic high level (VIH), output from the devices are disabled. This may cause the output pins
to be in a high impedance state.
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the device function.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The com-
mand register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the
falling edge of WE or CE, whichever starts later; while data is latched on the rising edge of WE or CE, whichever
starts first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Sector Group Protection
The device features hardware sector group protection. This feature will disable both program and erase opera-
tions in any combination of thirty two sector groups of memory.See “Sector Group Address Table
(MBM29PL32TM)” and “Sector Group Address Table (MBM29PL32BM)” in
■DEVICE BUS OPERATION. The
user‘s side can use the sector group protection using programming equipment. The device is shipped with all
sector groups that are unprotected.
To activate it, the programming equipment must force VID on address pin A9 and control pin OE, CE = VIL and
A6 = A3 = A2 = A0 = VIL, A1 = VIH. The sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13, and A12) should
be set to the sector to be protected. “Sector Address Table (MBM29PL32TM)” and “Sector Address Table
(MBM29PL32BM)” in
■DEVICE BUS OPERATION defines the sector address for each of the seventy-one (71)
individual sectors, and “Sector Group Address Table (MBM29PL32TM)” and “Sector Group Address Table
(MBM29PL32BM)” in
■DEVICE BUS OPERATION defines the sector group address for each of the twenty-four
(24) individual group sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse
and is terminated with the rising edge of the same. Sector group addresses must be held constant during the
WE pulse. See “Sector Group Protection Timing Diagram” in
■SWITCHING WAVEFORMS and “Sector Group
Protection Algorithm” in
■FLOW CHART for sector group protection timing diagram and algorithm.
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A20, A19, A18, A17, A16, A15, A14, A13,
and A12) while (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) will produce a logical “1” code at device output DQ0 for a
protected sector. Otherwise the device will produce “0” for unprotected sectors. In this mode, the lower order
addresses, except for A0, A1, A2, A3, and A6 can be either High or Low. Address locations with A1 = VIL are reserved
for Autoselect manufacturer and device codes. A-1 requires applying to VIL on Byte mode.
It is also possible to determine if a sector group is protected in the system by writing an Autoselect command.
Performing a read operation at the address location XX02h, where the higher order addresses(A20, A19, A18, A17,
A16, A15, A14, A13, and A12) are the desired sector group address will produce a logical “1” at DQ0 for a protected
sector group. See “Sector Group Protection Verify Autoselect Codes” in
■DEVICE BUS OPERATION for Au-
toselect codes.
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