
DS05-20825-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
FLASH MEMORY
CMOS
8M (1M
×
8)
MBM29LV008T/MBM29LV008B
I
FEATURES
Single 3.0 V read, program, and erase
Minimizes system level power requirements
Compatible with JEDEC-standard commands
Uses same software commands as E
Compatible with JEDEC-standard word-wide pinouts
40-pin TSOP (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
Minimum 100,000 write/erase cycles
High performance
100 ns maximum access time
Sector erase architecture
One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
Boot Code Sector Architecture
T = Top sector
B = Bottom sector
Embedded Erase
Algorithms
Automatically pre-programs and erases the chip or any sector
Embedded Program
Algorithms
Automatically writes and verifies data at specified address
Data Polling and Toggle Bit feature for detection of program or erase cycle completion
Ready-Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
Low power consumption
30 mA maximum active read current
35 mA maximum write/erase current
5
μ
A maximum standby current (CMOS Level)
250
μ
A maximum standby current (TTL/NMOS Compatible)
Low V
CC
write inhibit
≤
2.5 V
Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
2
PROMs
TM
TM
(Continued)
Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.