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| 型號(hào)： | MB9AF312MPMC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP80 |
| 封裝： | 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁(yè)數(shù)： | 108/114頁(yè) |
| 文件大?。?/td> | 1357K |
| 代理商： | MB9AF312MPMC |
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93
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
Table 15-6 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM mode.
Table 15-7 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode.
Bits 3, 2 – Reserved
These bits are reserved bits in the Atmel ATmega48PA/88PA/168PA and will always read as zero.
Bits 1:0 – WGM01:0: Waveform Generation Mode
Combined with the WGM02 bit found in the TCCR0B register, these bits control the counting sequence of the counter, the
source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 15-8. Modes of
operation supported by the Timer/Counter unit are: Normal mode (counter), clear timer on compare match (CTC) mode, and
two types of pulse width modulation (PWM) modes (see Section 15.7 “Modes of Operation” on page 86).
Table 15-6. Compare Output Mode, Fast PWM Mode(1)
COM0B1
COM0B0
Description
0
Normal port operation, OC0B disconnected.
0
1
Reserved
1
0
Clear OC0B on compare match, set OC0B at BOTTOM,(non-inverting mode)
1
Set OC0B on compare match, clear OC0B at BOTTOM,(inverting mode).
Note:
1.
A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the compare match is
ignored, but the set or clear is done at TOP. See Section 15.7.3 “Fast PWM Mode” on page 87 for more
details.
Table 15-7. Compare Output Mode, Phase Correct PWM Mode(1)
COM0B1
COM0B0
Description
0
Normal port operation, OC0B disconnected.
0
1
Reserved
1
0
Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match
when down-counting.
1
Set OC0B on Compare Match when up-counting. Clear OC0B on Compare Match
when down-counting.
Note:
1.
A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the compare match is
ignored, but the set or clear is done at TOP. See Section 15.7.4 “Phase Correct PWM Mode” on page 88 for
more details.
Table 15-8. Waveform Generation Mode Bit Description
Mode
WGM02
WGM01
WGM00
Timer/Counter
Mode of Operation
TOP
Update of
OCRx at
TOV Flag
Set on(1)(2)
0
Normal
0xFF
Immediate
MAX
1
0
1
PWM, phase
Correct
0xFF
TOP
BOTTOM
2
0
1
0
CTC
OCRA
Immediate
MAX
3
0
1
Fast PWM
0xFF
BOTTOM
MAX
4
1
0
Reserved
–
5
1
0
1
PWM, phase
Correct
OCRA
TOP
BOTTOM
6
1
0
Reserved
–
7
1
Fast PWM
OCRA
BOTTOM
TOP
Notes: 1.
MAX = 0xFF
2.
BOTTOM = 0x00
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