參數(shù)資料
型號: MB96F378HWBPMC-GSE2
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 56 MHz, MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù): 97/121頁
文件大?。?/td> 3362K
代理商: MB96F378HWBPMC-GSE2
PRELIMINARY
MB96370 Series
FME-MB96370 rev 5
77
4. AC Characteristics
Source Clock timing
(TA = -40C to 125C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter
Symbol
Pin
Value
Unit
Remarks
Min
Typ
Max
Clock frequency
fC
X0, X1
3
-
16
MHz When using a crystal oscillator, PLL off
0
-
16
MHz
When using an opposite phase external
clock, PLL off
3.5
-
16
MHz
When using a crystal oscillator or oppo-
site phase external clock, PLL on
Clock frequency
fFCI
X0
0
-
56
MHz
When using a single phase external
clock in “Fast Clock Input mode” , PLL off
3.5
-
56
MHz
When using a single phase external
clock in “Fast Clock Input mode” , PLL on
Clock frequency
fCL
X0A, X1A
32
32.768
100
kHz When using an oscillation circuit
0
-
100
kHz
When using an opposite phase external
clock
X0A
0
-
50
kHz
When using a single phase external
clock
Clock frequency
fCR
-
50
100
200
kHz
When using slow frequency of RC oscil-
lator
1
2
4
MHz
When using fast frequency of RC oscil-
lator
RC clock stabili-
zation time
tRCSTAB
-
64 RC clock cycles
Applied after any reset and when acti-
vating the RC oscillator.
PLL Clock fre-
quency
fCLKVCO
-
64
-
200
MHz
Permitted VCO output frequency of PLL
(CLKVCO)
PLL Phase Jitter
TPSKEW
--
-
± 5ns
For CLKMC (PLL input clock)
≥4MHz,
jitter coming from external oscillator,
crystal or resonator is not covered
Input clock pulse
width
PWH, PWL
X0,X1
8
-
ns
Duty ratio is about 30% to 70%
Input clock pulse
width
PWHL, PWLL
X0A,X1A
5
-
s
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