參數(shù)資料
型號： MB96F336UWAPMC-GSE2
廠商： FUJITSU COMPONENT LTD
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 48 MHz, MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, 0.50 MM PITCH, 1.70 MM HEIGHT, PLASTIC, LQFP-144
文件頁數(shù)： 7/124頁
文件大?。?/td> 3441K
代理商： MB96F336UWAPMC-GSE2
PRELIMINARY
MB96330 Series
104
FME-MB96330 rev 3
I2C Timing
*1 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHDDAT have only to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
*3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT
≥ 250 ns must then be met.
*4 : For use at over 100 kHz, set the peripheral clock 1 to at least 6 MHz.
(TA = -40C to 125C, VCC = AVCC = 3.0V to 5.5V,VSS = AVSS =0V)
Parameter
Symbol
Condition
Standard-mode
Fast-mode*4
Unit
Min
Max
Min
Max
SCL clock frequency
fSCL
R
= 1.7 k,
C
= 50 pF*1
0
100
0
400
kHz
Hold time (repeated) START condition
SDA
↓→SCL↓
tHDSTA
4.0
0.6
s
“L” width of the SCL clock
tLOW
4.7
1.3
s
“H” width of the SCL clock
tHIGH
4.0
0.6
s
Set-up time for a repeated START condition
SCL
↑→SDA↓
tSUSTA
4.7
0.6
s
Data hold time
SCL
↓→SDA↓↑
tHDDAT
0
3.45*2
0
0.9*3
s
Data set-up time
SDA
↓↑→SCL↑
tSUDAT
250
100
ns
Set-up time for STOP condition
SCL
↑→SDA↑
tSUSTO
4.0
0.6
s
Bus free time between a STOP and START
condition
tBUS
4.7
1.3
s
SDA
SCL
tLOW
tSUDAT
tHDSTA
tBUS
tHDSTA
tHDDAT
tHIGH
tSUSTA
tSUSTO
相關PDF資料
PDF描述
MB96F338USAPMC-GSE2 16-BIT, FLASH, 48 MHz, MICROCONTROLLER, PQFP144
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MB96F336USAPMC-GSE2 16-BIT, FLASH, 56 MHz, MICROCONTROLLER, PQFP144
MB96F338UWAPMC-GSE2 16-BIT, FLASH, 56 MHz, MICROCONTROLLER, PQFP144
相關代理商/技術參數(shù)
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