參數(shù)資料
型號(hào)： MB95R203PF-G-JNE2
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PDSO20
封裝： 12.70 X 7.50 MM, 1.27 MM PITCH, 2.65 MM HEIGHT, PLASTIC, SOP-20
文件頁(yè)數(shù)： 30/56頁(yè)
文件大小： 1935K
代理商： MB95R203PF-G-JNE2
MB95R203
36
DS07-12625-4E
(Continued)
(Vcc
= 3.3 V, Vss = 0.0 V, TA = 20 °C to +70 °C)
*1 : R, C : Pull-up resistance and load capacitance of the SCL and SDA lines.
*2 :
Refer to “ (2) Source Clock/Machine Clock” for details on tMCLK.
m is the CS4 and CS3 bits (bit 4 and bit 3) of the I2C clock control register (ICCR0) .
n is the CS2 to CS0 bits (bit 2 to bit0) of the I2C clock control register (ICCR0) .
The actual I2C timing is determined by the machine (tMCLK) and the values of m and n configured in bits
CS4 to CS0 of the I2C clock control register (ICCR0) .
Standard-mode :
m and n can be set in the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz.
The machine clock to be used is determined by the settings of m and n as follows.
(m, n)
= (1, 8)
: 0.9 MHz < tMCLK
≤ 1 MHz
(m, n)
= (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4)
: 0.9 MHz < tMCLK
≤ 2 MHz
(m, n)
= (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8)
: 0.9 MHz < tMCLK
≤ 4 MHz
(m, n)
= (1, 98)
: 0.9 MHz < tMCLK
≤ 1 MHz
Fast-mode :
m and n can be set in the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz.
The machine clock to be used is determined by the settings of m and n as follows.
(m, n)
= (1, 8)
: 3.3 MHz < tMCLK
≤ 4 MHz
(m, n)
= (1, 22) , (5, 4)
: 3.3 MHz < tMCLK
≤ 8 MHz
(m, n)
= (6, 4)
: 3.3 MHz < tMCLK
≤ 10 MHz
Parameter
Symbol
Pin
name
Condi-
tions
Value*2
Unit
Remarks
Min
Max
Stop condition
detection
tSU;STO
SCL
SDA
R
= 1.7 kΩ,
C
= 50 pF*1
4 tMCLK
20
ns
Undetected when 1
tMCLK is used at
reception
Restart condition
detection condition
tSU;STA
SCL
SDA
2 tMCLK
20
ns
Undetected when 1
tMCLK is used at
reception
Bus free time
tBUF
SCL
SDA
2 tMCLK
20
ns
During reception
Data hold time
tHD;DAT
SCL
SDA
2 tMCLK
20
ns
In slave transmission
mode
Data setup time
tSU;DAT
SCL
SDA
tLOW
3 tMCLK
20
ns
In slave transmission
mode
Data hold time
tHD;DAT
SCL
SDA
0
ns
During reception
Data setup time
tSU;DAT
SCL
SDA
tMCLK
20
ns
During reception
SDA
↓ → SCL ↑
(when using wakeup
function)
tWAKEUP
SCL
SDA
Oscillation
stabilization
wait time
+ 2
tMCLK
20
ns
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