參數(shù)資料
型號： MB95F416KPMC-G-SNE2
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù)： 57/84頁
文件大?。?/td> 3886K
代理商： MB95F416KPMC-G-SNE2
MB95310L/370L Series
60
DS07-12628-2E
(8) I2C Timing
(VCC = 3.0 V
±10%, AVSS = VSS = 0.0 V, TA = 40°C to +85°C)
*1: R represents the pull-up resistor of the SCL0 and SDA0 lines, and C the load capacitor of the SCL0 and
SDA0 lines.
*2: The maximum tHD;DAT in the Standard-mode is applicable only when the time during which the device is holding
the SCL signal at “L” (tLOW) does not extend.
*3: A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, provided that the condition
of tSU;DAT
≥ 250 ns is fulfilled.
(Continued)
Parameter
Symbol
Pin name
Conditions
Value
Unit
Standard-mode
Fast-mode
Min
Max
Min
Max
SCL clock
frequency
fSCL
SCL0
R = 1.7 k
Ω,
C = 50 pF*1
01000400
kHz
(Repeat)
Start
condition
hold time
SDA
↓ →
SCL
↓
tHD;STA
SCL0,
SDA0
4.0
—
0.6
—
s
SCL clock
“L” width
tLOW
SCL0
4.7
—
1.3
—
s
SCL clock
“H” width
tHIGH
SCL0
4.0
—
0.6
—
s
(Repeat)
Start
condition
setup time
SCL
↑ →
SDA
↓
tSU;STA
SCL0,
SDA0
4.7
—
0.6
—
s
Data hold
time
SCL
↓ →
SDA
↓ ↑
tHD;DAT
SCL0,
SDA0
0
3.45*2
00.9*3
s
Data setup
time
SDA
↓ ↑ →
SCL
↑
tSU;DAT
SCL0,
SDA0
0.25
—
0.1
—
s
Stop
condition
setup time
SCL
↑ →
SDA
↑
tSU;STO
SCL0,
SDA0
4.0
—
0.6
—
s
Bus free
time
between
stop
condition
and start
condition
tBUF
SCL0,
SDA0
4.7
—
1.3
—
s
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