參數(shù)資料
型號(hào): MB95F394HPMC-G-SNE2
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PQFP48
封裝: 7 X 7 MM, 0.50 MM PITCH, 1.70 MM HEIGHT, PLASTIC, LQFP-48
文件頁(yè)數(shù): 35/60頁(yè)
文件大?。?/td> 3064K
代理商: MB95F394HPMC-G-SNE2
MB95390H Series
40
DS07–12632–1E
(6) LIN-UART Timing
Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is disabled*2.
(ESCR register: SCES bit = 0, ECCR register: SCDE bit = 0)
(VCC = 5.0 V
±10%, AVSS = VSS = 0.0 V, TA = 40°C to +85°C)
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or
a falling edge of the serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3: See “(2) Source Clock/Machine Clock” for tMCLK.
Parameter
Symbol Pin name
Condition
Value
Unit
Min
Max
Serial clock cycle time
tSCYC
SCK
Internal clock
operation output pin:
CL = 80 pF
+ 1 TTL
5 tMCLK*3
—ns
SCK
↓ → SOT delay time
tSLOVI
SCK, SOT
95
+95
ns
Valid SIN
→ SCK ↑
tIVSHI
SCK, SIN
tMCLK*3
+ 190
ns
SCK
↑ → valid SIN hold time
tSHIXI
SCK, SIN
0
ns
Serial clock “L” pulse width
tSLSH
SCK
External clock
operation output pin:
CL = 80 pF
+ 1 TTL
3 tMCLK*3
tR
—ns
Serial clock “H” pulse width
tSHSL
SCK
tMCLK*3
+ 95
ns
SCK
↓ → SOT delay time
tSLOVE
SCK, SOT
2 tMCLK*3
+ 95 ns
Valid SIN
→ SCK ↑
tIVSHE
SCK, SIN
190
ns
SCK
↑ → valid SIN hold time
tSHIXE
SCK, SIN
tMCLK*3
+ 95
ns
SCK fall time
tF
SCK
10
ns
SCK rise time
tR
SCK
10
ns
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MB95F394KPMC-G-SNE2 功能描述:IC MCU 8BIT 20KB FLASH 48LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器, 系列:F²MC MB95390H 標(biāo)準(zhǔn)包裝:250 系列:LPC11Uxx 核心處理器:ARM? Cortex?-M0 芯體尺寸:32-位 速度:50MHz 連通性:I²C,Microwire,SPI,SSI,SSP,UART/USART,USB 外圍設(shè)備:欠壓檢測(cè)/復(fù)位,POR,WDT 輸入/輸出數(shù):40 程序存儲(chǔ)器容量:96KB(96K x 8) 程序存儲(chǔ)器類型:閃存 EEPROM 大小:4K x 8 RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):1.8 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:48-LQFP 包裝:托盤 其它名稱:568-9587