參數(shù)資料
型號(hào): MB95F333HWQN-G-SNE1
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PQCC32
封裝: 5 X 5 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, PLASTIC, QFN-32
文件頁(yè)數(shù): 10/68頁(yè)
文件大?。?/td> 4600K
代理商: MB95F333HWQN-G-SNE1
18
DS07–12629–1E
MB95330H Series
■ BLOCK DIAGRAM
Reset with LVD
Flash with security function
(20/12/8 Kbyte)
F2MC-8FX CPU
RAM (1008/496/240 bytes)
Oscillator
circuit
CR
oscillator
Clock control
On-chip debug
Wild register
External interrupt
Interrupt controller
LIN-UART
8/16-bit composite timer ch. 0
8/10-bit A/D converter
16-bit reload timer
MPG
16-bit PPG
8/16-bit PPG ch. 1
8/16-bit composite timer ch. 1
Waveform sequencer
UART/SIO
I2C
8/16-bit PPG ch. 0
8/16-bit PPG ch. 2
Port
PF2*1/RST*2
PF1/X1*2
PF0/X0*2
(PG2/X1A*2)
(PG1/X0A*2)
(P04/HCLK1)
(P05/HCLK2)
P02/INT02 to P07/INT07
C
(P02/SCK)
(P03/SOT)
(P04/SIN)
(P14/UCK0)
(P15/UO0)
(P16/UI0)
(P62/PPG00*3), P13/PPG00
(P63/PPG01*3), P14/PPG01
(P66/PPG20*3), P15/PPG20
(P67/PPG21*3), P16/PPG21
(P60/SDA*1)
(P61/SCL*1)
P00/INT00, P01/INT01,
P60/INT08, P61/INT09
(P12/DBG*1)
(P05/TO00)
(P06/TO01)
P12/EC0, (P04/EC0)
(P00/AN00 to P07/AN07)
(P62/TO10)
(P63/TO11)
(P64/EC1)
(P61/TI1)
(P17/TO1)
P62/OPT0 to P67/OPT5*3
P17/SNI0, PG1/SNI1, PG2/SNI2
(P60/DTTI)
(P61/TI1)
(P67/TRG1)
(P66/PPG1)
P10/PPG10, (P64/PPG10*3)
P11/PPG11, (P65/PPG11*3)
Vcc
Vss
*1:
*2:
*3:
PF2, P12, P60 and P61 are N-ch open drain pins.
Software option
P62 to P67 are high-current pins.
Inter
n
a
l
bu
s
Note: Pins in parentheses indicate that functions of those pins are shared among different resources.
相關(guān)PDF資料
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MB95F332KP-G-SH-SNE2 MICROCONTROLLER, PDIP32
MB95F334KP-G-SH-SNE2 MICROCONTROLLER, PDIP32
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