參數(shù)資料
型號: MB95F274HPF-G-SNE2
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, MICROCONTROLLER, PDSO8
封裝: 5.30 X 5.24 MM, 2.10 MM HEIGHT, 1.27 MM PITCH, PLASTIC, SOP-8
文件頁數(shù): 87/92頁
文件大?。?/td> 3535K
代理商: MB95F274HPF-G-SNE2
MB95260H/270H/280H Series
88
DS07–12627–5E
■ MAIN CHANGES IN THIS EDITION
(Continued)
Page
Section
Change Results
49
■ ELECTRICAL CHARACTERISTICS
3. DC Characteristics
Changed the maximum value of the open-drain output
application voltage.
0.2 VCC
→ Vss + 5.5
53
4. AC Characteristics
(1) Clock Timing
Changed the following footnote as follows.
*2: These specifications are not applicable to the following
products: MB95F262HWQN, MB95F262KWQN,
MB95F263HWQN, MB95F263KWQN, MB95F264HWQN,
MB95F264KWQN, MB95F272HPH, MB95F272KPH,
MB95F273HPH, MB95F273KPH, MB95F274HPH,
MB95F274KPH, MB95F282HPH,
MB95F282KPH,MB95F283HPH, MB95F283KPH,
MB95F284HPH , MB95F284KPH, MB95F282HWQN,
MB95F282KWQN, MB95F283HWQN, MB95F283KWQN,
MB95F284HWQN and MB95F284KWQN.
*2: These specifications are not applicable to the following
products: MB95F272HPH, MB95F272KPH, MB95F273HPH,
MB95F273KPH, MB95F274HPH, MB95F274KPH,
MB95F282HPH, MB95F282KPH, MB95F283HPH,
MB95F283KPH, MB95F284HPH , MB95F284KPH.
*3: These specifications are only applicable to the following
products: MB95F262HWQN, MB95F262KWQN,
MB95F263HWQN, MB95F263KWQN, MB95F264HWQN,
MB95F264KWQN, MB95F272HPH, MB95F272KPH,
MB95F273HPH, MB95F273KPH, MB95F274HPH,
MB95F274KPH, MB95F282HPH, MB95F282KPH,
MB95F283HPH, MB95F283KPH, MB95F284HPH ,
MB95F284KPH, MB95F282HWQN, MB95F282KWQN,
MB95F283HWQN, MB95F283KWQN, MB95F284HWQN
and MB95F284KWQN.
*3: These specifications are only applicable to the following
products: MB95F272HPH, MB95F272KPH, MB95F273HPH,
MB95F273KPH, MB95F274HPH, MB95F274KPH,
MB95F282HPH, MB95F282KPH, MB95F283HPH,
MB95F283KPH, MB95F284HPH and MB95F284KPH.
54
Added the figure for circuit in “
Figure of main clock input
port external connection”.
55
(2) Source Clock / Machine Clock
Corrected the remarks of symbol tSCLK in “Source clock cycle
time” as follows.
(When the sub-oscillation clock is used
→ When the sub CR
clock is used)
56
Corrected the figure for “
Schematic diagram of the clock
generation block”.
(Added “Machine clock division ratio select bits (SYCC:
DIV1, DIV0)”)
57
(3) External Reset
Corrected the remarks of “RST “L” level pulse width”.
(and watch mode
→ watch mode, and power-on)
相關PDF資料
PDF描述
MB95F284HPH-G-SNE2 8-BIT, FLASH, MICROCONTROLLER, PDIP16
MB95F263HPFT-G-SNE2 8-BIT, FLASH, MICROCONTROLLER, PDSO20
MB95F333HWQN-G-SNE1 MICROCONTROLLER, PQCC32
MB95F332KP-G-SH-SNE2 MICROCONTROLLER, PDIP32
MB95F334KP-G-SH-SNE2 MICROCONTROLLER, PDIP32
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