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參數(shù)資料
| 型號(hào)： | MB95F128NB |
| 廠商： | Fujitsu Limited |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT SINGLE CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁(yè)數(shù)： | 59/80頁(yè) |
| 文件大?。?/td> | 1488K |
| 代理商： | MB95F128NB |
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MB95120MB Series
59
(V
CC
=
5.0 V
±
10
%
, AV
SS
=
V
SS
=
0.0 V, T
A
=
40
°
C to
+
105
°
C)
Value*
2
Min
Max
(Continued)
Parameter
Sym-
bol
Pin
name
Condition
Unit
Remarks
SCL clock
“L” width
SCL clock
“H” width
t
LOW
SCL0
R
=
1.7 k
,
C
=
50 pF*
1
(2
+
nm
/
2) t
MCLK
20
ns
Master mode
t
HIGH
SCL0
(nm
/
2) t
MCLK
20
(nm
/
2 ) t
MCLK
+
20
ns
Master mode
Start condition
hold time
t
HD;STA
SCL0
SDA0
(
1
+
nm
/
2) t
MCLK
20
(
1
+
nm) t
MCLK
+
20
ns
Master mode
Maximum value is
applied when m,
n
=
1, 8.
Otherwise, the
minimum value is
applied.
Stop condition
setup time
Start condition
setup time
Bus free time
between stop
condition and
start condition
t
SU;STO
SCL0
SDA0
SCL0
SDA0
(1
+
nm
/
2) t
MCLK
20 (1
+
nm
/
2) t
MCLK
+
20
ns
Master mode
t
SU;STA
(1
+
nm
/
2) t
MCLK
20 (1
+
nm
/
2) t
MCLK
+
20
ns
Master mode
t
BUF
SCL0
SDA0
(2 nm
+
4) t
MCLK
20
ns
Data hold time t
HD;DAT
SCL0
SDA0
3 t
MCLK
20
ns
Master mode
Data setup
time
t
SU;DAT
SCL0
SDA0
(
2
+
nm
/
2) t
MCLK
20 (
1
+
nm
/
2) t
MCLK
+
20
ns
Master mode
When assuming
that “L” of SCL is
not extended, the
minimum value is
applied to first bit
of continuous
data.
Otherwise,
the maximum
value is applied.
Minimum value is
applied to interrupt
at 9th SCL
↓
.
Maximum value is
applied to interrupt
at 8th SCL
↓
.
Setup time
between
clearing
interrupt and
SCL rising
t
SU;INT
SCL0
(nm
/
2) t
MCLK
20
(1 + nm
/
2) t
MCLK
+
20
ns
SCL clock “L”
width
SCL clock “H”
width
t
LOW
SCL0
4 t
MCLK
20
ns
At reception
t
HIGH
SCL0
4 t
MCLK
20
ns
At reception
Start condition
detection
t
HD;STA
SCL0
SDA0
2 t
MCLK
20
ns
Undetected when
1 t
MCLK
is used at
reception
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