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參數(shù)資料
| 型號(hào)： | MB95F126MB |
| 廠商： | Fujitsu Limited |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT SINGLE CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁(yè)數(shù)： | 44/80頁(yè) |
| 文件大小： | 1488K |
| 代理商： | MB95F126MB |
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MB95120MB Series
44
(2) Source Clock/Machine Clock
(V
CC
=
5.0 V
±
10
%
, AV
SS
=
V
SS
=
0.0 V, T
A
=
40
°
C to
+
105
°
C)
Value
Unit
Min
Max
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This
source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it becomes
the machine clock. Further, the source clock can be selected as follows.
Main clock divided by 2
PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication)
Sub clock divided by 2
PLL multiplication of sub clock (select from 2, 3, 4 multiplication)
*
2
: Operation clock of the microcontroller. Machine clock can be selected as follows.
Source clock (no division)
Source clock divided by 4
Source clock divided by 8
Source clock divided by 16
Parameter
Symbol
Condi-
tion
Remarks
Source clock cycle time*
1
(Clock before setting
division)
t
SCLK
61.5
2000
ns
When using main clock
Min : F
CH
=
8.125 MHz,
PLL multiplied by 2
Max : F
CH
=
1 MHz, divided by 2
When using sub clock
Min : F
CL
=
32 kHz,
PLL multiplied by 4
Max : F
CL
=
32 kHz, divided by 2
MHz When using main clock
7.6
61.0
μ
s
Source clock frequency
F
SP
0.50
16.25
F
SPL
16.384
131.072
kHz When using sub clock
Machine clock cycle time*
2
(Minimum instruction
execution time)
t
MCLK
61.5
32000
ns
When using main clock
Min : F
SP
=
16.25 MHz, no division
Max : F
SP
=
0.5 MHz, divided by 16
When using sub clock
Min : F
SPL
=
131 kHz, no division
Max : F
SPL
=
16 kHz, divided by 16
MHz When using main clock
7.6
976.5
μ
s
Machine clock frequency
F
MP
0.031
16.250
F
MPL
1.024
131.072
kHz When using sub clock
F
CH
(main oscillation)
F
CL
(sub oscillation)
Divided by 2
Main PLL
×
1
×
2
×
2.5
×
4
Divided by 2
Sub PLL
×
2
×
3
×
4
SCLK
(source clock)
Clock mode select bit
(SYCC: SCS1, SCS0)
MCLK
(machine clock)
Division
circuit
×
1
×
1/4
×
1/8
×
1/16
Outline of clock generation block
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB95F126NB | 8-BIT SINGLE CHIP MICROCONTROLLERS |
| MB95F134MBS | 8-BIT SINGLE CHIP MICROCONTROLLERS |
| MB95F133JBS | 8-BIT SINGLE CHIP MICROCONTROLLERS |
| MB95F133JBW | 8-BIT SINGLE CHIP MICROCONTROLLERS |
| MB95F133MBS | 8-BIT SINGLE CHIP MICROCONTROLLERS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB95F126MBPF | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Microcontrollers |
| MB95F126MBPMC | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Microcontrollers |
| MB95F126NB | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Microcontrollers |
| MB95F126NBPF | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Microcontrollers |
| MB95F126NBPMC | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Microcontrollers |
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