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參數(shù)資料
| 型號： | MB95F106ANW |
| 廠商： | Fujitsu Limited |
| 英文描述： | 8-bit Proprietary Microcontrollers(8位微控制器) |
| 中文描述： | 8位微控制器專利（8位微控制器） |
| 文件頁數(shù)： | 24/72頁 |
| 文件大小： | 739K |
| 代理商： | MB95F106ANW |
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MB95100AM Series
24
The RP indicates the address of the register bank currently being used. The relationship between the content
of RP and the real address conforms to the conversion rule illustrated below:
Rule for Conversion of Actual Addresses in the General-purpose Register Area
The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct
addresses to 0080
H
to 00FF
H
.
Direct bank pointer (DP2 to DP0)
Specified address area
XXX
B
(no effect to mapping)
0000
H
to 007F
H
000
B
(initial value)
001
B
010
B
011
B
100
B
101
B
110
B
111
B
The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that
control CPU operations at interrupt.
Mapping area
0000
H
to 007F
H
(without mapping)
0080
H
to 00FF
H
(without mapping)
0100
H
to 017F
H
0180
H
to 01FF
H
0200
H
to 027F
H
0280
H
to 02FF
H
0300
H
to 037F
H
0380
H
to 03FF
H
0400
H
to 047F
H
0080
H
to 00FF
H
H flag
: Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.
Cleared to “0” otherwise. This flag is for decimal adjustment instructions.
: Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”.
The flag is set to “0” when reset.
IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level
is higher than the value indicated by this bit.
I flag
IL1
0
0
1
IL0
0
1
0
Interrupt level
0
1
2
Priority
High
Low = no interruption
1
1
3
N flag
:
Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the
bit is set to “0”.
:
Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise.
:
Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0”
otherwise.
:
Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared
to “0” otherwise. Set to the shift-out value in the case of a shift instruction.
Z flag
V flag
C flag
"0"
"0"
"0"
"0"
"0"
"0"
"0"
"1"
R4
R3
R2
R1
R0
b2
b1
b0
A7
A6
A5
A4
A3
A2
A1
A0
A15
A14 A13 A12 A11 A10
A9
A8
Generated address
RP upper
OP code lower
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB95F106ANWPFM | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontrollers |
| MB95F106ANWPFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontrollers |
| MB95F106JSPFM-GE1 | 制造商:FUJITSU 功能描述:8BIT MCU 32K FLASH 1K RAM QFP64 |
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