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參數(shù)資料
| 型號(hào)： | MB95F104AMS |
| 廠商： | Fujitsu Limited |
| 英文描述： | 8-bit Proprietary Microcontrollers(8位微控制器) |
| 中文描述： | 8位微控制器專(zhuān)利（8位微控制器） |
| 文件頁(yè)數(shù)： | 57/72頁(yè) |
| 文件大小： | 739K |
| 代理商： | MB95F104AMS |
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MB95100AM Series
57
(Vcc
=
5.0 V
±
10
%
, AVss
=
Vss
=
0.0 V, T
A
=
40
°
C to
+
85
°
C)
Value*
2
Min
Max
(Continued)
Parameter
Sym-
bol
Pin
nameCondition
Unit
Remarks
SCL clock “L” width
t
LOW
SCL0
R
=
1.7 k
,
C
=
50 pF*
1
(2
+
nm
/
2) t
MCLK
20
ns
Master mode
SCL clock “H” width
t
HIGH
SCL0
(nm
/
2) t
MCLK
20
(nm
/
2 ) t
MCLK
+
20
ns
Master mode
Start condition hold
time
t
HD;STA
SCL0
SDA0
(
1
+
nm
/
2) t
MCLK
20
(
1
+
nm) t
MCLK
+
20
ns
Master mode
Maximum value is
applied when m, n
=
1, 8.
Otherwise, the minimum
value is applied.
Stop condition setup
time
t
SU;STO
SCL0
SDA0
(1
+
nm
/
2) t
MCLK
20 (1
+
nm
/
2) t
MCLK
+
20
ns
Master mode
Start condition setup
time
t
SU;STA
SCL0
SDA0
(1
+
nm
/
2) t
MCLK
20 (1
+
nm
/
2) t
MCLK
+
20
ns
Master mode
Bus free time between
stop condition and
start condition
t
BUF
SCL0
SDA0
(2 nm
+
4) t
MCLK
20
ns
Data hold time
t
HD;DAT
SCL0
SDA0
3 t
MCLK
20
ns
Master mode
Data setup time
t
SU;DAT
SCL0
SDA0
(
2
+
nm
/
2) t
MCLK
20 (
1
+
nm
/
2) t
MCLK
+
20
ns
Master mode
When assuming that “L”
of SCL is not extended,
the minimum value is
applied to first bit of
continuous data.
Otherwise, the maximum
value is applied.
Setup time between
clearing interrupt and
SCL rising
t
SU;INT
SCL0
(nm
/
2) t
MCLK
20
(1 + nm
/
2) t
MCLK
+
20
ns
Minimum value is
applied to interrupt at 9th
SCL
↓
.
Maximum value is
applied to interrupt at 8th
SCL
↓
.
At reception
SCL clock “L” width
t
LOW
SCL0
4 t
MCLK
20
ns
SCL clock “H” width
t
HIGH
SCL0
4 t
MCLK
20
ns
At reception
Start condition
detection
t
HD;STA
SCL0
SDA0
2 t
MCLK
20
ns
Undetected when 1 t
MCLK
is used at reception
Stop condition
detection
t
SU;STO
SCL0
SDA0
2 t
MCLK
20
ns
Undetected when 1 t
MCLK
is used at reception
Restart detection
condition
t
SU;STA
SCL0
SDA0
2 t
MCLK
20
ns
Undetected when 1 t
MCLK
is used at reception
Bus free time
t
BUF
SCL0
SDA0
2 t
MCLK
20
ns
At reception
Data hold time
t
HD;DAT
SCL0
SDA0
2 t
MCLK
20
ns
At slave transmission
mode
Data setup time
t
SU;DAT
SCL0
SDA0
t
LOW
3 t
MCLK
20
ns
At slave transmission
mode
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|---|---|
| MB95F104AMSPFM | 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontrollers |
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| MB95F104AMWPFM | 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontrollers |
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