參數(shù)資料
型號: MB91302APFF-G-010-BNDE1
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 32-BIT, MROM, 68 MHz, RISC MICROCONTROLLER, PQFP144
封裝: 0.40 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù): 77/96頁
文件大?。?/td> 2641K
代理商: MB91302APFF-G-010-BNDE1
MB90520B Series
DS07-13707-5E
87
(5) UART (SCI) Timings
(AVCC
= VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = 40 °C to +85 °C)
* : See “ (3) Clock Timings” for more information about tCP (internal operating clock cycle time) .
Notes :
These are the AC ratings for CLK synchronous mode.
CL is the load capacitor connected to the pin for testing.
Parameter
Sym-
bol
Pin Name
Condition
Value
Unit
Min
Typ
Serial clock cycle time
tSCYC
SCK0 to SCK2
Internal shift clock
mode, output pin load
is
CL
= 80 pF + 1 TTL
8 tCP*
ns
SCK
↓ → SOT delay time
tSLOV
SCK0 to SCK2
SOT0 to SOT2
80
ns
Valid SIN
→ SCK ↑
tIVSH
SCK0 to SCK2
SIN0 to SIN2
100
ns
SCK
↑ → valid SIN hold time
tSHIX
SCK0 to SCK2
SIN0 to SIN2
60
ns
Serial clock “H” pulse width
tSHSL
SCK0 to SCK2
External shift clock
mode, output pin load
is
CL
= 80 pF + 1 TTL
4 tCP*
ns
Serial clock “L” pulse width
tSLSH
SCK0 to SCK2
4 tCP*
ns
SCK
↓ → SOT delay time
tSLOV
SCK0 to SCK2
SOT0 to SOT2
150
ns
Valid SIN
→ SCK ↑
tIVSH
SCK0 to SCK2
SIN0 to SIN2
60
ns
SCK
↑ → valid SIN hold time
tSHIX
SCK0 to SCK2
SIN0 to SIN2
60
ns
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