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參數(shù)資料
| 型號(hào)： | MB91192LGA |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-bit Proprietary Microcontroller |
| 中文描述： | 32-BIT, MROM, 20 MHz, RISC MICROCONTROLLER, PBGA144 |
| 封裝： | PLASTIC, FLGA-144 |
| 文件頁(yè)數(shù)： | 21/33頁(yè) |
| 文件大?。?/td> | 435K |
| 代理商： | MB91192LGA |
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MB
91191/192 Series
21
(2) Multiplex Bus Read/Write Operation
(V
DD
=
+
3.0 V
±
0.3 V, V
SS
=
AV
SS
=
0 V, T
A
=
20
°
C to
+
70
°
C)
Value
*1 : When the bus is delayed by automatic wait insertion, add (t
CYC
×
number of wait cycles) to this value.
*2 : This value is for gear setting
=
×
1
For the value for gear settings 1/2, 1/4, and 1/8, substitute 1/2, 1/4, and 1/8 respectively for n in the formula below.
Formula : t
CYCH
=
(1
n
/
2)
×
t
CYC
t
CYCL
=
(n
/
2)
×
t
CYC
Parameter
Symbol
Pin Name
Condi-
tion
Unit
Re-
marks
Min
Typ
t
CYCH
Max
ALE pulse width
t
EHEL
ALE
t
CYC
10
t
CYCH
15
t
CYCL
2
t
CYC
11
t
CYC
11
t
CYC
11
t
CYC
11
15
ns
Address delay time
t
EHAV
A15 to A0
,
D31 to D16
t
CYCH
+
15
t
CYCL
+
10
t
CYCL
+
26
t
CYC
+
11
t
CYC
+
11
t
CYC
+
11
t
CYC
+
11
ns
*2
Address clear time
t
EHAX
t
CYCL
t
CYC
ns
*2
Data delay time
t
ELDV
D31 to D16
ns
*2
RD delay time
t
ELRL
RD
ns
RD pulse width
t
RLRH
t
CYC
ns
*1
WR0, WR1 delay time
t
ELWL
WR0, WR1
t
CYC
ns
WR0, WR1 pulse width
Data setup
→
RD
↑
time
RD
↑→
Data hold time
t
WLWH
t
CYC
ns
*1
t
DSRH
RD
,
D31 to D16
ns
t
RHDX
0
ns
t
WLWH
Internal
clock
ALE
Read time
D31 to D16
MPX bus
RD
Write time
D31 to D16
MPX bus
WR0 , WR1
A15 to A08
When not
multiplexed
t
EHEL
t
EHAV
t
ELAX
t
DSRH
t
RHDX
t
ELRL
t
RLRH
t
ELDV
t
WHDX
t
ELWL
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