參數(shù)資料
型號: MB90V595CR
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 16 MHz, MICROCONTROLLER, CPGA256
封裝: CERAMIC, PGA-256
文件頁數(shù): 25/47頁
文件大?。?/td> 674K
代理商: MB90V595CR
MB90595/595G Series
31
*1: The interrupt request flag is cleared by the EI2OS interrupt clear signal.
*2: The interrupt request flag is cleared by the EI2OS interrupt clear signal. A stop request is available.
N/A:The interrupt request flag is not cleared by the EI2OS interrupt clear signal.
Note:
For a peripheral module with two interrupt for a single interrupt number, both interrupt request flags
are cleared by the EI2OS interrupt clear signal.
At the end of EI2OS, the EI2OS clear signal will be asserted for all the interrupt flags assigned to the same
interrupt number. If one interrupt flag starts the EI2OS and in the meantime another interrupt flag is set by
hardware event, the later event is lost because the flag is cleared by the EI2OS clear signal caused by the
first event. So it is recommended not to use the EI2OS for this interrupt number.
If EI2OS is enabled, EI2OS is initiated when one of the two interrupt signals in the same interrupt control
register (ICR) is asserted. This means that different interrupt sources share the same EI2OS Descriptor
which should be unique for each interrupt source. For this reason, when one interrupt source uses the
EI2OS, the other interrupt should be disabled.
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