參數(shù)資料
型號(hào): MB90V590ACR
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 16 MHz, MICROCONTROLLER, CPGA256
封裝: CERAMIC, PGA-256
文件頁數(shù): 39/52頁
文件大?。?/td> 718K
代理商: MB90V590ACR
MB90590/590G Series
44
(4) UART0/1/2, Serial I/O
(MB90V590A, MB90F594A, MB90594, MB90V590G, MB90F594G, MB90594G:
VCC
= 5.0 V±10 %, VSS = AVSS = 0.0 V, TA = 40 °C to +85 °C)
(MB90F591A, MB90591: VCC
= 5.0 V±5 %, VSS = AVSS = 0.0 V, TA = 40 °C to +85 °C)
*: tCP is the machine cycle (Unit: ns)
Notes:
AC characteristic in CLK synchronized mode.
CL is load capacity value of pins when testing.
Parameter
Symbol
Pin name
Condition
Value
Unit
Remarks
Min.
Max.
Serial clock cycle time
tSCYC
SCK0 to SCK3
Internal clock opera-
tion output pins are
CL = 80 pF + 1 TTL.
8 tCP*—
ns
SCK
↓ SOT delay time
tSLOV
SCK0 to SCK3,
SOT0 to SOT3
–80
80
ns
Valid SIN
SCK ↑
tIVSH
SCK0 to SCK3,
SIN0 to SIN3
100
ns
SCK
↑ Valid SIN hold time
tSHIX
SCK0 to SCK3,
SIN0 to SIN3
60
ns
Serial clock "H" pulse width
tSHSL
SCK0 to SCK3
External clock oper-
ation output pins are
CL = 80 pF + 1 TTL.
4 tCP
—ns
Serial clock "L" pulse width
tSLSH
SCK0 to SCK3
4 tCP
—ns
SCK
↓ SOT delay time
tSLOV
SCK0 to SCK3,
SOT0 to SOT3
150
ns
Valid SIN
SCK ↑
tIVSH
SCK0 to SCK3,
SIN0 to SIN3
60
ns
SCK
↑ Valid SIN hold time
tSHIX
SCK0 to SCK3,
SIN0 to SIN3
60
ns
SCK
2.4 V
tSCYC
0.8 V
SOT
0.8 V
2.4 V
0.8 V
tSLOV
SIN
0.6 VCC
0.8 VCC
tIVSH
0.6 VCC
0.8 VCC
tSHIX
Internal Shift Clock Mode
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