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參數資料
| 型號： | MB90V570 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 16-bit Proprietary Microcontroller |
| 中文描述： | 16位微控制器專有 |
| 文件頁數： | 75/135頁 |
| 文件大?。?/td> | 2504K |
| 代理商： | MB90V570 |
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75
MB90570 Series
17. Address Match Detection Function
When the address is equal to a value set in the address detection register, the instruction code loaded into the
CPU is replaced forcibly with the INT9 instruction code (01H). As a result, when the CPU executes a set
instruction, the INT9 instruction is executed. Processing by the INT#9 interrupt routine allows the program
patching function to be implemented.
Two address detection registers are supported. An interrupt enable bit is prepared for each register. If the value
set in the address detection register matches an address and if the interrupt enable bit is set at “1”, the instruction
code loaded into the CPU is replaced forcibly with the INT9 instruction code.
(1) Register Configuration
Program address detection register 0 to 2 (PADR0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXX
B
R/W: Readable and writable
X : Undefined
RESV: Reserved bit
Address
PADR0 (Low order address): 001FF0
H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXX
B
Address
PADR0 (Middle order address): 001FF1
H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXX
B
Address
PADR0 (High order address): 001FF2
H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXX
B
Address
PADR1 (Low order address): 001FF3
H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXX
B
Address
PADR1 (Middle order address): 001FF4
H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
XXXXXXXX
B
Address
PADR1 (High order address): 001FF5
H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Initial value
00000000
B
Address
00009E
H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Program address detection register 3 to 5 (PADR1)
Program address detection control status register (PACSR)
RESV
RESV
RESV
RESV
AD1E
RESV
AD0E
RESV
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