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參數資料
| 型號： | MB90V420G |
| 廠商： | Fujitsu Limited |
| 英文描述： | 16-Bit Original Microcontroller |
| 中文描述： | 16位微控制器原件 |
| 文件頁數： | 38/99頁 |
| 文件大?。?/td> | 1706K |
| 代理商： | MB90V420G |
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MB90420G/5G (A) Series
38
3.
Input Capture
This circuit is composed of a 16-bit free-run timer and four 16-bit input capture circuits.
(1) Input capture (
×
4)
The input capture circuits consist of four independent external input pins and corresponding capture registers
and control registers. When the specified edge of the external signal input (at the input pin) is detected, the value
of the 16-bit free-run timer is saved in the capture register, and at the same time an interrupt can also be
generated.
The valid edge (rising edge, falling edge, both edges) of the external signal can be selected.
The four input capture circuits can operate independently.
The interrupt can be generated from the valid edge of the external input signal.
(2) 16-bit free-run timer (
×
1)
The 16-bit free-run timer is composed of a 16-bit up-counter, control register, 16-bit compare register, and
prescaler. The output values from this counter are used as the base time for the input capture circuits.
The counter clock operation can be selected from 8 options. The eight internal clock settings are
φ
,
φ
/2,
φ
/4,
φ
/8,
φ
/16,
φ
/32,
φ
/64,
φ
/128 where
φ
represents the machine clock cycle.
Interrupts can be generated from overflow events, or from compare match events with the compare register.
(Compare match operation requires a mode setting.)
The counter value can be initialized to “0000
H
” by a reset, soft clear, or a compare match with the compare
register.
(3) Block diagram
IVF
IVFE
STOP MODE SCLR CLK2 CLK1 CLK0
φ
MSI3
～
0
ICLR
EG11
EG10
EG01
EG00
ICRE
IN0/2
IN1/3
ICP0
ICP1
ICE0
ICE1
interrupt
#31 (1F
H
)
Divider
Clock
16-bit free-run timer
F
2
M
16-bit compare clear register
Compare circuit
Interrupt
#33 (21
H
)
A/D startup
Capture data register 0/2
Capture data register 1/3
Edge detection
Edge detection
Interrupt
#19
,
#23
Interrupt
#15
,
#21
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