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參數(shù)資料
| 型號(hào)： | MB90V390HCR |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 24 MHz, MICROCONTROLLER, CPGA299 |
| 封裝： | CERAMIC, PGA-299 |
| 文件頁(yè)數(shù)： | 61/74頁(yè) |
| 文件大?。?/td> | 886K |
| 代理商： | MB90V390HCR |
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MB90390 Series
64
(9) I2C Timing
(TA
= 40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V)
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHDDAT only has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
*3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT
≥ 250 ns must then be met.
*4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.
Parameter
Symbol
Condition
Standard-mode
Fast-mode*4
Unit
Min
Max
Min
Max
SCL clock frequency
fSCL
R
= 1.3 k,
C
= 50 pF*1
0
100
0
400
kHz
Hold time (repeated) START condition
SDA
↓ → SCL ↓
tHDSTA
4.0
0.6
s
“L” width of the SCL clock
tLOW
4.7
1.3
s
“H” width of the SCL clock
tHIGH
4.0
0.6
s
Set-up time for a repeated START condition
SCL
↑ → SDA ↓
tSUSTA
4.7
0.6
s
Data hold time
SCL
↓ → SDA ↓ ↑
tHDDAT
0
3.45*2
00.9*3
s
Data set-up time
SDA
↓ ↑ → SCL ↑
tSUDAT
250
100
ns
Set-up time for STOP condition
SCL
↑ → SDA ↑
tSUSTO
4.0
0.6
s
Bus free time between a STOP and START
condition
tBUS
4.7
1.3
s
SDA
SCL
tLOW
tSUDAT
tHDSTA
tBUS
tHDSTA
tHDDAT
tHIGH
tSUSTA
tSUSTO
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