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參數(shù)資料
| 型號： | MB90T553A |
| 廠商： | Fujitsu Limited |
| 英文描述： | Quadruple Bus Buffer Gates With 3- State Outputs 20-LCCC -55 to 125 |
| 中文描述： | 16位微控制器專有 |
| 文件頁數(shù)： | 41/58頁 |
| 文件大小： | 695K |
| 代理商： | MB90T553A |
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MB90550A/550B Series
41
(8) Hold Timing
(V
CC
=
5.0 V
±
10%, V
SS
=
AV
SS
=
0.0 V, T
A
=
40
°
C to +85
°
C)
Value
Note : More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched.
(9) UART, Extended I/O Serial 0, 1 Timing
(V
CC
=
5.0 V
±
10%, V
SS
=
AV
SS
=
0.0 V, T
A
=
40
°
C to +85
°
C)
Notes: These are AC ratings in the CLK synchronous mode.
C
L
is the load capacitance value connected to pins while testing.
Parameter
Symbol
Pin name
Unit
Remarks
Min.
Max.
Pins in floating status
→
HAK
↓
time
HAK
↑
→
pin valid time
t
XHAL
HAK
30
t
CP
ns
t
HAHV
t
CP
2 t
CP
ns
Parameter
Symbol
Pin name
Condition
Value
Unit
Remarks
Min.
Max.
Serial clock cycle time
t
SCYC
SCK0 to SCK2
Internal shift clock
mode
C
L
= 80 pF
+ 1 TTL for an out-
put pin
8 t
CP
—
ns
SCK
↓ →
SOT delay time
t
SLOV
SCK0 to SCK2,
SOT0 to SOT2
–80
80
ns
Valid SIN
→
SCK
↑
t
IVSH
SCK0 to SCK2,
SIN0 to SIN2
100
—
ns
SCK
↑ →
valid SIN hold time
t
SHIX
SCK0 to SCK2,
SIN0 to SIN2
t
CP
—
ns
Serial clock “H” pulse width
t
SHSL
SCK0 to SCK2
External shift clock
mode
C
L
= 80 pF
+ 1 TTL for an
output pin
4 t
CP
—
ns
Serial clock “L” pulse width
t
SLSH
SCK0 to SCK2
4 t
CP
—
ns
SCK
↓ →
SOT delay time
t
SLOV
SCK0 to SCK2,
SOT0 to SOT2
—
150
ns
Valid SIN
→
SCK
↑
t
IVSH
SCK0 to SCK2,
SIN0 to SIN2
60
—
ns
SCK
↑ →
valid SIN hold time
t
SHIX
SCK0 to SCK2,
SIN0 to SIN2
60
—
ns
HAK
t
XHAL
t
HAHV
Pins
High impedance
Hold timing
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