![](http://datasheet.mmic.net.cn/330000/MB90T678_datasheet_16438155/MB90T678_114.png)
MB90670/675 Series
114
Table 17 Shift Instructions (Byte/Word/Long Word) [18 Instructions]
*1: 6 when R0 is 0, 5 + (R0) in all other cases.
*2: 6 when R0 is 0, 6 + (R0) in all other cases.
Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”
and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”
Mnemonic
#
~
R
G
B
Operation
L
H
A
H
I
S
T
N
Z
V
C
RM
W
RORCA
ROLCA
RORCear
RORCeam
ROLCear
ROLCeam
ASR A, R0
LSR
LSL
A, R0
A, R0
2
2
2
2+
2
2+
2
2
2
2
2
3
5+
(a)
3
5+
(a)
*
1
*
1
*
1
0
0
2
0
2
0
1
1
1
0
0
0
2
×
(b)
0
2
×
(b)
0
0
0
byte (A)
←
Right rotation with carry
byte (A)
←
Left rotation with carry
byte (ear)
←
Right rotation with carry
byte (eam)
←
Right rotation with
carry
byte (ear)
←
Left rotation with carry
byte (eam)
←
Left rotation with carry
byte (A)
←
Arithmetic right barrel shift (A,
R0)
byte (A)
←
Logical right barrel shift
(A, R0)
byte (A)
←
Logical left barrel shift (A,
R0)
word (A)
←
Arithmetic right shift (A, 1
bit)
word (A)
←
Logical right shift (A, 1
bit)
word (A)
←
Logical left shift (A, 1 bit)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
–
–
–
*
–
*
–
–
–
ASRWA
LSRWA/SHRW
A
LSLW A/SHLW
A
ASRWA, R0
LSRWA, R0
LSLW A, R0
1
1
1
2
2
2
2
2
2
*
1
*
1
*
1
0
0
0
1
1
1
0
0
0
0
0
0
word (A)
←
Arithmetic right barrel shift (A,
R0)
word (A)
←
Logical right barrel shift
(A, R0)
word (A)
←
Logical left barrel shift (A,
R0)
long (A)
←
Arithmetic right shift (A,
R0)
long (A)
←
Logical right barrel shift
(A, R0)
long (A)
←
Logical left barrel shift (A,
R0)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
–
*
R
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
ASRL A, R0
LSRL A, R0
LSLL A, R0
2
2
2
*
2
*
2
*
2
1
1
1
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–