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參數(shù)資料
| 型號(hào)： | MB90P663A |
| 廠商： | Fujitsu Limited |
| 英文描述： | 16-bit Proprietary Microcontroller |
| 中文描述： | 16位微控制器專有 |
| 文件頁(yè)數(shù)： | 41/84頁(yè) |
| 文件大小： | 1440K |
| 代理商： | MB90P663A |
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41
MB90660A Series
8. Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate an interrupt for task switching. If this module is
used, an interrupt request to the F
2
MC-16L CPU can be generated or cancelled by software.
(1) Register Configuration
The DIRR register controls the generation and cancellation of delayed interrupt requests. A delayed interrupt
request is generated when “1” is written to this register, while a delayed interrupt request is cancelled when “0”
is written here. Request cancel status results upon reset. Although either “0” or “1” may be written into reserved
bits, we recommend using the set bit and clear bit instructions when accessing this register in consideration of
possible future extensions.
(2) Block Diagram
bit
Read/Write
Initial value
–
–
–
–
–
–
–
R0
DIRR
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(R/W)
(0)
15
14
13
12
11
10
9
8
Delayed interrupt request
generation/cancel register
Address: 000009
H
Delayed interrupt source generation/
cancel decoder
Source latch
F
2
M
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